Datasheet

KSZ9031RNX
DS00002117F-page 57  2016-2017 Microchip Technology Inc.
7.0 TIMING DIAGRAMS
7.1 RGMII Timing
As the default, after power-up or reset, the KSZ9031RNX RGMII timing conforms to the timing requirements in the
RGMII Version 2.0 Specification for internal PHY chip delay.
For the transmit path (MAC to KSZ9031RNX), the KSZ9031RNX does not add any delay locally at its GTX_CLK, TX_EN
and TXD[3:0] input pins, and expects the GTX_CLK delay to be provided on-chip by the MAC. If MAC does not provide
any delay or insufficient delay for the GTX_CLK, the KSZ9031RNX has pad skew registers that can provide up to
1.38 ns on-chip delay.
For the receive path (KSZ9031RNX to MAC), the KSZ9031RNX adds 1.2 ns typical delay to the RX_CLK output pin
with respect to RX_DV and RXD[3:0] output pins. If necessary, the KSZ9031RNX has pad skew registers that can adjust
the RX_CLK on-chip delay up to 2.58 ns from the 1.2 ns default delay.
It is common to implement RGMII PHY-to-MAC designs that either PHY, MAC, or both PHY and MAC are not fully RGMII
v2.0 compliant with on-chip clock delay. These combinations of mixed RGMII v1.3/v2.0 designs and plus sometimes
non-matching RGMII PCB trace routings require a review of the entire RGMII system timings (PHY on-chip, PCB trace
delay, MAC on-chip) to compute the aggregate clock delay and determine if the clock delay timing is met. If timing adjust-
ment is needed, pad skew registers are provided by the KSZ9031RNX. Refer to RGMII Pad Skew Registers section.
The following Figure 7-1, Figure 7-2, and Table 7-1 from the RGMII v2.0 Specification are provided as references to
understanding RGMII v1.3 external delay and RGMII v2.0 on-chip delay timings.
FIGURE 7-1: RGMII V2.0 SPEC (MULTIPLEXING AND TIMING DIAGRAM – ORIGINAL RGMII
(V1.3) WITH EXTERNAL DELAY)