Datasheet

KSZ9031RNX
DS00002117F-page 46  2016-2017 Microchip Technology Inc.
2.2.9 Reserved Reserved RW 0
2.2.8 PME_N1
Output
Enable
For LED1/PME_N1 (Pin 17),
1 = Enable PME output
0 = Disable PME output
This bit works in conjunction with MMD Address
2h, Reg. 10h, Bits [15:14] to define the output for
Pin 17.
RW 0
2.2.7 Chip Power-
Down
Override
1 = Override strap-in for chip power-down mode RW Set by MODE[3:0]
strapping pin.
See the Strap-In
Options -
KSZ9031RNX
section for details.
2.2.6:5 Reserved Reserved RW 00
2.2.4 NAND Tree
Override
1 = Override strap-in for NAND Tree mode RW Set by MODE[3:0]
strapping pin.
See the Strap-In
Options -
KSZ9031RNX
section for details.
2.2.3:0 Reserved Reserved RW 0000
MMD Address 2h, Register 3h – Operation Mode Strap Status
2.3.15 RGMII All
Capabilities
Strap-In
Status
1 = Strap to RGMII to advertise all capabilities RO
Set by MODE[3:0]
strapping pin.
See the Strap-In
Options -
KSZ9031RNX
section for details.
2.3.14 RGMII No
1000BT_HD
Strap-In
Status
1 = Strap to RGMII to advertise all capabilities
except 1000BASE-T half-duplex
RO
2.3.13 RGMII Only
1000BT_H/
FD Strap-In
Status
1 = Strap to RGMII to advertise 1000BASE-T full-
and half-duplex only
RO
2.3.12 RGMII Only
1000BT_FD
Strap-In
Status
1 = Strap to RGMII to advertise 1000BASE-T full-
duplex only
RO
2.3.11:8 Reserved Reserved RO 0000
2.3.7 Chip Power-
Down Strap-
In Status
1 = Strap to chip power-down mode RO Set by MODE[3:0]
strapping pin.
See the Strap-In
Options -
KSZ9031RNX
section for details.
2.3.6:5 Reserved Reserved RO 00
TABLE 4-6: MMD REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description
Mode
Note 4-1
Default