Datasheet
2016-2017 Microchip Technology Inc. DS00002117F-page 33
KSZ9031RNX
4.2 Standard Registers
Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE
802.3 Specification. Within this address space, the first 16 registers (Registers 0h to Fh) are defined according to the
IEEE specification, while the remaining 16 registers (Registers 10h to 1Fh) are defined specific to the PHY vendor.
2h
24h Wake-On-LAN – Customized Packet, Type 2, Mask 0
25h Wake-On-LAN – Customized Packet, Type 2, Mask 1
26h Wake-On-LAN – Customized Packet, Type 2, Mask 2
27h Wake-On-LAN – Customized Packet, Type 2, Mask 3
28h Wake-On-LAN – Customized Packet, Type 3, Mask 0
29h Wake-On-LAN – Customized Packet, Type 3, Mask 1
2Ah Wake-On-LAN – Customized Packet, Type 3, Mask 2
2Bh Wake-On-LAN – Customized Packet, Type 3, Mask 3
1Ch
4h Analog Control 4
23h EDPD Control
TABLE 4-3: IEEE-DEFINED REGISTER DESCRIPTIONS
Address Name Description
Mode
Note 4-1
Default
Register 0h – Basic Control
0.15 Reset 1 = Software PHY reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
RW/SC 0
0.14 Loopback 1 = Loopback mode
0 = Normal operation
RW 0
0.13 Speed Select
(LSB)
[0.6, 0.13]
[1,1] = Reserved
[1,0] = 1000 Mbps
[0,1] = 100 Mbps
[0,0] = 10 Mbps
This bit is ignored if auto-negotiation is enabled
(Reg. 0.12 = 1).
RW 0
0.12 Auto-Negoti-
ation Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
If enabled, auto-negotiation result overrides set-
tings in Reg. 0.13, 0.8 and 0.6.
If disabled, Auto MDI-X is also automatically dis-
abled. Use Register 1Ch to set MDI/MDI-X.
RW 1
0.11 Power-Down 1 = Power-down mode
0 = Normal operation
When this bit is set to ‘1’, the link-down status
might not get updated in the PHY register. Software
should note link is down and should not rely on the
PHY register link status.
After this bit is changed from ‘1’ to ‘0’, an internal
global reset is automatically generated. Wait a min-
imum of 1 ms before read/write access to the PHY
registers.
RW 0
TABLE 4-2: MMD REGISTERS SUPPORTED BY KSZ9031RNX (CONTINUED)
Device Address (hex) Register Address (hex) Description