Datasheet

 2016-2017 Microchip Technology Inc. DS00002117F-page 23
KSZ9031RNX
• Write value 0x03FF (delay GTX_CLK and RX_CLK pad skews to their maximum values) to MMD Address 2h,
Register 8h
- Write Register 0xD = 0x0002 // Select MMD Device Address 2h
- Write Register 0xE = 0x0008 // Select Register 8h of MMD Device Address 2h
- Write Register 0xD = 0x4002 // Select register data for MMD Device Address 2h, Register 8h
- Write Register 0xE = 0x03FF // Write value 0x03FF to MMD Device Address 2h, Register 8h
3.9.4 RGMII IN-BAND STATUS
The KSZ9031RNX provides in-band status to the MAC during the inter-frame gap when RX_DV is de-asserted. RGMII
in-band status is always enabled after power-up.
The in-band status is sent to the MAC using the RXD[3:0] data pins, and is described in Ta b l e 3-7.
3.10 MII Management (MIIM) Interface
The KSZ9031RNX supports the IEEE 802.3 MII management interface, also known as the Management Data Input/
Output (MDIO) interface. This interface allows upper-layer devices to monitor and control the state of the KSZ9031RNX.
An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. More details
about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the physical connection mentioned earlier, which allows an external con-
troller to communicate with one or more KSZ9031RNX devices. Each KSZ9031RNX device is assigned a unique
PHY address between 0h and 7h by the PHYAD[2:0] strapping pins.
• A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for indi-
rect access to MMD addresses and registers. See the Register Map section.
PHY Address 0h is supported as the unique PHY address only; it is not supported as the broadcast PHY address, which
allows for a single write command to simultaneously program an identical PHY register for two or more PHY devices
(for example, using PHY Address 0h to set Register 0h to a value of 0x1940 to set Bit [11] to a value of one to enable
software power-down). Instead, separate write commands are used to program each PHY device.
Table 3-8 shows the MII management frame format for the KSZ9031RNX.
3.11 Interrupt (INT_N)
The INT_N pin is an optional interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ9031RNX PHY register. Bits [15:8] of Register 1Bh are the interrupt control bits that enable and dis-
able the conditions for asserting the INT_N signal. Bits [7:0] of Register 1Bh are the interrupt status bits that indicate
which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.
Bit [14] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.
TABLE 3-7: RGMII IN-BAND STATUS
RX_DV RXD3 RXD[2:1] RXD0
0
(valid only when RX_DV is
low)
Duplex Status
0 = Half-duplex
1 = Full-duplex
RX_CLK clock speed
00 =
2.5 MHz (10 Mbps)
01 =
25 MHz (100 Mbps)
10 =
125 MHz (1000 Mbps)
11 = Reserved
Link Status
0 = Link down
1 = Link up
TABLE 3-8: MII MANAGEMENT FRAME FORMAT FOR THE KSZ9031RNX
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA Data Bits [15:0] Idle
Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z