Datasheet

 2016-2017 Microchip Technology Inc. DS00002117F-page 19
KSZ9031RNX
During the speed transition, the receive clock is stretched on either a positive or negative pulse to ensure that no
clock glitch is presented to the MAC.
• TX_ER and RX_ER are combined with TX_EN and RX_DV, respectively, to form TX_CTL and RX_CTL. These
two RGMII control signals are valid at the falling clock edge.
After power-up or reset, the KSZ9031RNX is configured to RGMII mode if the MODE[3:0] strap-in pins are set to one of
the RGMII mode capability options. See the Strap-In Options - KSZ9031RNX section.
The KSZ9031RNX has the option to output a 125 MHz reference clock on the CLK125_NDO pin. This clock provides a
lower-cost reference clock alternative for RGMII MACs that require a 125 MHz crystal or oscillator. The 125 MHz clock
output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.
3.9.1 RGMII SIGNAL DEFINITION
Table 3-3 describes the RGMII signals. Refer to the RGMII Version 2.0 Specification for more detailed information.
3.9.2 RGMII SIGNAL DIAGRAM
The KSZ9031RNX RGMII pin connections to the MAC are shown in Figure 3-4.
FIGURE 3-4: KSZ9031RNX RGMII INTERFACE
TABLE 3-3: RGMII SIGNAL DEFINITION
RGMII Signal
Name (per spec)
RGMII Signal
Name (per
KSZ9031RNX)
Pin Type (with
respect to PHY)
Pin Type (with
respect to MAC)
Description
TXC GTX_CLK Input Output Transmit Reference Clock
(125MHz for 1000Mbps, 25MHz for
100Mbps, 2.5MHz for 10Mbps)
TX_CTL TX_EN Input Output Transmit Control
TXD[3:0] TXD[3:0] Input Output Transmit Data[3:0]
RXC RX_CLK Output Input Receive Reference Clock
(125 MHz for 1000 Mbps, 25 MHz
for 100 Mbps, 2.5 MHz for
10 Mbps)
RX_CTL RX_DV Output Input Receive Control
RXD[3:0] RXD[3:0] Output Input Receive Data[3:0]
KSZ9031RNX
GTX _CLK
TX _EN
TXD[3:0]
RX_CLK
RX _DV
RXD
[3:0]
GMII
ETHERNET MAC
TXC
TX _CTL
TXD[3:0]
RXC
RX _CTL
RXD
[3:0]
R