KSZ9031RNX Gigabit Ethernet Transceiver with RGMII Support Features • Single-Chip 10/100/1000 Mbps Ethernet Transceiver Suitable for IEEE 802.3 Applications • RGMII Timing Supports On-Chip Delay According to RGMII Version 2.0, with Programming Options for External Delay and Making Adjustments and Corrections to TX and RX Timing Paths • RGMII with 3.3V/2.5V/1.
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KSZ9031RNX Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Pin Description and Configuration .................................................................................................................................................. 5 3.0 Functional Description ....................................................................
KSZ9031RNX 1.0 INTRODUCTION 1.1 General Description The KSZ9031RNX is a completely integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physicallayer transceiver for transmission and reception of data on standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ9031RNX provides the Reduced Gigabit Media Independent Interface (RGMII) for direct connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at 10/100/1000 Mbps.
KSZ9031RNX PIN DESCRIPTION AND CONFIGURATION XI XO AVDDL_PLL LDO_O RESET_N CLK125_NDO/ LED_MODE DVDDH DVDDL INT_N/ PME_N2 MDIO 48-QFN PIN ASSIGNMENT (TOP VIEW) NC FIGURE 2-1: ISET 2.
KSZ9031RNX TABLE 2-1: SIGNALS - KSZ9031RNX Pin Number Pin Name Type Note 2-1 1 AVDDH P 2 TXRXP_A I/O Media Dependent Interface[0], negative signal of differential pair 1000BASE-T mode: TXRXM_A corresponds to BI_DA– for MDI configuration and BI_DB– for MDI-X configuration, respectively. 10BASE-T/100BASE-TX mode: TXRXM_A is the negative transmit signal (TX–) for MDI configuration and the negative receive signal (RX–) for MDI-X configuration, respectively.
KSZ9031RNX TABLE 2-1: Pin Number 10 SIGNALS - KSZ9031RNX (CONTINUED) Pin Name TXRXP_D Type Note 2-1 Description I/O Media Dependent Interface[3], positive signal of differential pair 1000BASE-T mode: TXRXP_D corresponds to BI_DD+ for MDI configuration and BI_DC+ for MDI-X configuration, respectively. 10BASE-T/100BASE-TX mode: TXRXP_D is not used.
KSZ9031RNX TABLE 2-1: Pin Number SIGNALS - KSZ9031RNX (CONTINUED) Pin Name Type Note 2-1 Description LED output: Programmable LED2 output Config mode: The pull-up/pull-down value is latched as PHYAD[1] during power-up/reset. See the Strap-In Options - KSZ9031RNX section for details.
KSZ9031RNX TABLE 2-1: Pin Number SIGNALS - KSZ9031RNX (CONTINUED) Pin Name Type Note 2-1 Description LED1 output: Programmable LED1 output Config mode: The voltage on this pin is sampled and latched during the power-up/reset process to determine the value of PHYAD[0]. See the Strap-In Options - KSZ9031RNX section for details. PME_N output: Programmable PME_N output (pin option 1). This pin function requires an external pull-up resistor to DVDDH (digital VDD_I/O) in a range from 1.0 kΩ to 4.7 kΩ.
KSZ9031RNX TABLE 2-1: SIGNALS - KSZ9031RNX (CONTINUED) Pin Number Pin Name Type Note 2-1 25 TX_EN I RGMII mode: RGMII TX_CTL (Transmit Control) input 26 DVDDL P 1.2V digital VDD 27 RXD3/ MODE3 I/O RGMII mode: RGMII RD3 (Receive Data 3) output Config mode: The pull-up/pull-down value is latched as MODE3 during power-up/reset. See the Strap-In Options - KSZ9031RNX section for details.
KSZ9031RNX TABLE 2-1: Pin Number SIGNALS - KSZ9031RNX (CONTINUED) Pin Name Type Note 2-1 Description 41 CLK125_NDO/ LED_MODE I/O 125 MHz clock output This pin provides a 125 MHz reference clock output option for use by the MAC. Config mode: The pull-up/pull-down value is latched as LED_MODE during power-up/reset. See the Strap-In Options - KSZ9031RNX section for details.
KSZ9031RNX Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during power-up or reset, and consequently cause the PHY strap-in pins on the RGMII signals to be latched to an incorrect configuration. In this case, external pull-up or pull-down resistors should be added on the PHY strap-in pins to ensure the PHY is configured to the correct pin strap-in mode.
KSZ9031RNX 3.0 FUNCTIONAL DESCRIPTION The KSZ9031RNX is a completely integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physical layer transceiver solution for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ9031RNX reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core.
KSZ9031RNX Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit compensates for the effect of baseline wander and improves the dynamic range. The differential data conversion circuit converts the MLT-3 format back to NRZI. The slicing threshold is also adaptive. The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format.
KSZ9031RNX FIGURE 3-2: KSZ9031RNX 1000BASE-T BLOCK DIAGRAM - SINGLE CHANNEL XTAL OTHER CHANNELS CLOCK GENERATION TX SIGNAL SIDE -STREAM SCRAMBLER AND SYMBOL ENCODER TRANSMIT BLOCK PCS STATE MACHINES LED DRIVER NEXT CANCELLER NEXT Canceller NEXT Canceller ECHO CANCELLER ANALOG HYBRID PAIR SWAP AND ALIGN UNIT BASELINE WANDER COMPENSATION RXADC AGC RX SIGNAL FFE + CLOCK AND PHASE RECOVERY AUTO NEGOTIATION DESCRAMBLER + DECODER SLICER DFE MII REGISTERS MII MANAGEMENT CONTROL PMA STATE MA
KSZ9031RNX In 10BASE-T/100BASE-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and recover the channel loss from the incoming data. 3.2.6 TRELLIS ENCODER AND DECODER In 1000BASE-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5 symbols. The initial scrambler seed is determined by the specific PHY address to reduce EMI when more than one KSZ9031RNX is used on the same board.
KSZ9031RNX 3.7 Auto-Negotiation The KSZ9031RNX conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification. Auto-negotiation allows UTP (unshielded twisted pair) link partners to select the highest common mode of operation. During auto-negotiation, link partners advertise capabilities across the UTP link to each other, and then compare their own capabilities with those they received from their link partners.
KSZ9031RNX After auto-negotiation is completed, the link status is updated in Register 1h, Bit [2], and the link partner capabilities are updated in Registers 5h, 6h, 8h, and Ah. The auto-negotiation finite state machines use interval timers to manage the auto-negotiation process. The duration of these timers under normal operating conditions is summarized in Table 3-2.
KSZ9031RNX During the speed transition, the receive clock is stretched on either a positive or negative pulse to ensure that no clock glitch is presented to the MAC. • TX_ER and RX_ER are combined with TX_EN and RX_DV, respectively, to form TX_CTL and RX_CTL. These two RGMII control signals are valid at the falling clock edge. After power-up or reset, the KSZ9031RNX is configured to RGMII mode if the MODE[3:0] strap-in pins are set to one of the RGMII mode capability options.
KSZ9031RNX 3.9.3 RGMII PAD SKEW REGISTERS Pad skew registers are available for all RGMII pins (clocks, control signals, and data bits) to provide programming options to adjust or correct the timing relationship for each RGMII pin. Because RGMII is a source-synchronous bus interface, the timing relationship needs to be maintained only within the RGMII pin’s respective timing group.
KSZ9031RNX TABLE 3-5: ABSOLUTE DELAY FOR 5-BIT PAD SKEW SETTING Pad Skew Value Delay (ns) 0_0000 –0.90 0_0001 –0.84 0_0010 –0.78 0_0011 –0.72 0_0100 –0.66 0_0101 –0.60 0_0110 –0.54 0_0111 –0.48 0_1000 –0.42 0_1001 –0.36 0_1010 –0.30 0_1011 –0.24 0_1100 –0.18 0_1101 –0.12 0_1110 –0.06 0_1111 No delay adjustment (default value) 1_0000 +0.06 1_0001 +0.12 1_0010 +0.18 1_0011 +0.24 1_0100 +0.30 1_0101 +0.36 1_0110 +0.42 1_0111 +0.48 1_1000 +0.54 1_1001 +0.
KSZ9031RNX TABLE 3-6: ABSOLUTE DELAY FOR 4-BIT PAD SKEW SETTING Pad Skew Value Delay (ns) 0000 –0.42 0001 –0.36 0010 –0.30 0011 –0.24 0100 –0.18 0101 –0.12 0110 –0.06 0111 No delay adjustment (default value) 1000 +0.06 1001 +0.12 1010 +0.18 1011 +0.24 1100 +0.30 1101 +0.36 1110 +0.42 1111 +0.
KSZ9031RNX • Write value 0x03FF (delay GTX_CLK and RX_CLK pad skews to their maximum values) to MMD Address 2h, Register 8h - Write Register 0xD = 0x0002 // Select MMD Device Address 2h - Write Register 0xE = 0x0008 // Select Register 8h of MMD Device Address 2h - Write Register 0xD = 0x4002 // Select register data for MMD Device Address 2h, Register 8h - Write Register 0xE = 0x03FF // Write value 0x03FF to MMD Device Address 2h, Register 8h 3.9.
KSZ9031RNX The MII management bus option gives the MAC processor complete access to the KSZ9031RNX control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change. 3.12 LED Mode The KSZ9031RNX provides two programmable LED output pins, LED2 and LED1, which are configurable to support two LED modes. The LED mode is configured by the LED_MODE strap-in (Pin 41).
KSZ9031RNX 3.13 Loopback Mode The KSZ9031RNX supports the following loopback operations to verify analog and/or digital data paths. • Local (digital) loopback • Remote (analog) loopback 3.13.1 LOCAL (DIGITAL) LOOPBACK This loopback mode checks the RGMII transmit and receive data paths between KSZ9031RNX and external MAC, and is supported for all three speeds (10/100/1000 Mbps) at full-duplex. The loopback data path is shown in Figure 3-5. 1. 2. 3. RGMII MAC transmits frames to KSZ9031RNX.
KSZ9031RNX FIGURE 3-6: REMOTE (ANALOG) LOOPBACK KSZ9031RNX RJ-45 AFE (ANALOG) PCS (DIGITAL) RGMII CAT-5 (UTP) RJ-45 1000BASE-T LINK PARTNER The following programming steps and register settings are used for remote loopback mode. 1. Set Register 0h, - Bits [6, 13] = 10 // Select 1000 Mbps speed - Bit [12] = 0 // Disable auto-negotiation - Bit [8] = 1 // Select full-duplex mode Or just auto-negotiate and link up at 1000BASE-T full-duplex mode with the link partner. 2.
KSZ9031RNX TABLE 3-11: 3.16 NAND TREE TEST PIN ORDER FOR KSZ9031RNX (CONTINUED) Pin Description GTX_CLK Input TX_EN Input RX_DV Input RX_CLK Input INT_/PME_N2 Input MDC Input MDIO Input CLK125_NDO Output Power Management The KSZ9031RNX incorporates a number of power-management modes and features that provide methods to consume less energy. These are discussed in the following sections. 3.16.
KSZ9031RNX 3.17.1 MAGIC-PACKET DETECTION The magic packet’s frame format starts with 6 bytes of 0xFFh and is followed by 16 repetitions of the MAC address of its associated MAC device (local MAC device). When the magic packet is detected from its link partner, the KSZ9031RNX asserts its PME output pin low.
KSZ9031RNX 3.17.
KSZ9031RNX TABLE 3-14: TYPICAL CURRENT/POWER CONSUMPTION TRANSCEIVER (2.5V; Note 3-1), DIGITAL I/O (2.5V) 1.2V Core (DVDDL, AVDDL, AVDDL_PLL) 2.5V Transceiver (AVDDH) 2.5V Digital I/O (DVDDH) Total Chip Power 1000BASE-T Link-Up (no traffic) 210 mA 58.8 mA 14.7 mA 435 mW 1000BASE-T Full-Duplex at 100% Utilization 221 mA 57.9 mA 31.5 mA 488 mW 100BASE-TX Link-Up (no traffic) 63.6 mA 24.9 mA 10.5 mA 165 mW 100BASE-TX Full-Duplex at 100% Utilization 63.8 mA 24.9 mA 13.
KSZ9031RNX 4.0 REGISTER DESCRIPTIONS This chapter describes the various control and status registers (CSRs). 4.1 Register Map The register space within the KSZ9031RNX consists of two distinct areas. • Standard registers • MDIO Manageable device (MMD) registers // Direct register access // Indirect register access The KSZ9031RNX supports the following standard registers.
KSZ9031RNX TABLE 4-2: MMD REGISTERS SUPPORTED BY KSZ9031RNX Device Address (hex) 0h 1h 2h DS00002117F-page 32 Register Address (hex) Description 3h AN FLP Burst Transmit – LO 4h AN FLP Burst Transmit – HI 5Ah 1000BASE-T Link-Up Time Control 0h Common Control 1h Strap Status 2h Operation Mode Strap Override 3h Operation Mode Strap Status 4h RGMII Control Signal Pad Skew 5h RGMII RX Data Pad Skew 6h RGMII TX Data Pad Skew 8h GMII Clock Pad Skew 10h Wake-On-LAN – Control 11h Wak
KSZ9031RNX TABLE 4-2: MMD REGISTERS SUPPORTED BY KSZ9031RNX (CONTINUED) Device Address (hex) Register Address (hex) 2h 1Ch 4.
KSZ9031RNX TABLE 4-3: Address IEEE-DEFINED REGISTER DESCRIPTIONS (CONTINUED) Name Description 0.10 Isolate 1 = Electrical isolation of PHY from RGMII 0 = Normal operation 0.9 0.8 Mode Note 4-1 Default RW 0 Restart Auto- 1 = Restart auto-negotiation process Negotiation 0 = Normal operation This bit is self-cleared after a ‘1’ is written to it. RW/SC 0 Duplex Mode 1 = Full-duplex 0 = Half-duplex RW 1 0.7 Reserved RW 0 0.6 Speed Select [0.6, 0.
KSZ9031RNX TABLE 4-3: Address 2.15:0 IEEE-DEFINED REGISTER DESCRIPTIONS (CONTINUED) Name Description PHY ID Number Assigned to Bits [3:18] of the organizationally unique identifier (OUI). KENDIN Communication’s OUI is 0010A1h. Mode Note 4-1 Default RO 0022h Register 3h - PHY Identifier 2 3.15:10 PHY ID Number Assigned to Bits [19:24] of the organizationally unique identifier (OUI). KENDIN Communication’s OUI is 0010A1h. RO 0001_01 3.
KSZ9031RNX TABLE 4-3: Address IEEE-DEFINED REGISTER DESCRIPTIONS (CONTINUED) Name Description 5.11:10 Pause [5.11, 5.10] [0,0] = No pause [1,0] = Asymmetric Pause (link partner) [0,1] = Symmetric pause [1,1] = Symmetric and asymmetric pause (local device) 5.9 Mode Note 4-1 Default RW 00 100BASE-T4 1 = T4 capable 0 = No T4 capability RO 0 5.8 100BASE-TX 1 = 100 Mbps full-duplex capable Full-Duplex 0 = No 100 Mbps full-duplex capability RO 0 5.
KSZ9031RNX TABLE 4-3: Address IEEE-DEFINED REGISTER DESCRIPTIONS (CONTINUED) Name Description 8.15 Next Page 1 = Additional next pages will follow 0 = Last page 8.14 Mode Note 4-1 Default RO 0 Acknowledge 1 = Successful receipt of link word 0 = No successful receipt of link word RO 0 8.13 Message Page 1 = Message page 0 = Unformatted page RO 0 8.12 Acknowledge2 1 = Able to act on the information 0 = Not able to act on the information RO 0 8.
KSZ9031RNX TABLE 4-3: Address IEEE-DEFINED REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default 9.9 1000BASE-T 1 = Advertise PHY is 1000BASE-T full-duplex Full-Duplex capable 0 = Advertise PHY is not 1000BASE-T full-duplex capable RW 1 9.8 1000BASE-T 1 = Advertise PHY is 1000BASE-T half-duplex Half-Duplex capable 0 = Advertise PHY is not 1000BASE-T half-duplex capable RW Set by MODE[3:0] strapping pins. See the Strap-In Options KSZ9031RNX section for details. 9.
KSZ9031RNX TABLE 4-3: Address D.4:0 IEEE-DEFINED REGISTER DESCRIPTIONS (CONTINUED) Name Description MMD – Device Address These five bits set the MMD device address. Mode Note 4-1 Default RW 0_0000 RW 0000_0000_0000_00 00 Register Eh - MMD Access – Register/Data E.15:0 MMD – Register/ Data For the selected MMD device address (Reg. Dh, Bits [4:0]), When Reg. Dh, Bits [15:14] = 00, this register contains the read/write register address for the MMD device address.
KSZ9031RNX TABLE 4-4: Address 12.13:12 VENDOR-SPECIFIC REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default Cable Diagnostic Test Pair These two bits select the differential pair for testing: RW 00 = Differential pair A (Pins 2, 3) 01 = Differential pair B (Pins 5, 6) 10 = Differential pair C (Pins 7, 8) 11 = Differential pair D (Pins 10, 11) 00 12.11:10 Reserved These two bits should always be set to ‘00’. RW 00 12.
KSZ9031RNX TABLE 4-4: Address VENDOR-SPECIFIC REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default 1B.9 Remote Fault 1 = Enable remote fault interrupt Interrupt 0 = Disable remote fault interrupt Enable RW 0 1B.8 Link-Up Interrupt Enable RW 0 1B.7 Jabber Inter- 1 = Jabber occurred rupt 0 = Jabber did not occur RO/RC 0 1B.6 Receive Error Interrupt 1 = Receive error occurred 0 = Receive error did not occur RO/RC 0 1B.
KSZ9031RNX TABLE 4-4: Address VENDOR-SPECIFIC REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default 1F.6 Speed 1 = Indicate chip final speed status at 1000BASE-T RO Status 1000BASE-T 0 1F.5 Speed 1 = Indicate chip final speed status at 100BASE-TX RO Status 100BASE-TX 0 1F.4 Speed Status 10BASE-T 1 = Indicate chip final speed status at 10BASE-T RO 0 1F.3 Duplex Status Indicate chip duplex status 1 = Full-duplex 0 = Half-duplex RO 0 1F.
KSZ9031RNX 4.3 MMD Registers MMD registers provide indirect read/write access to up to 32 MMD device addresses with each device supporting up to 65,536 16-bit registers, as defined in Clause 22 of the IEEE 802.3 Specification. The KSZ9031RNX, however, uses only a small fraction of the available registers. See the Register Map section for a list of supported MMD device addresses and their associated register addresses.
KSZ9031RNX TABLE 4-6: Address MMD REGISTER DESCRIPTIONS Name Description Mode Note 4-1 Default MMD Address 0h, Register 3h – AN FLP Burst Transmit – LO 0.3.15:0 AN FLP Burst Transmit – LO This register and the following register set the Auto-Negotiation FLP burst transmit timing. The same timing must be set for both registers. 0x4000 = Select 8 ms interval timing (default) 0x1A80 = Select 16 ms interval timing All other values are reserved.
KSZ9031RNX TABLE 4-6: Address MMD REGISTER DESCRIPTIONS (CONTINUED) Mode Note 4-1 Name Description Default 2.0.1 CLK125_EN Status Override strap-in for CLK125_EN 1 = CLK125_EN strap-in is enabled 0 = CLK125_EN strap-in is disabled RW Set by CLK125_EN strapping pin. See the Strap-In Options KSZ9031RNX section for details. 2.0.0 Reserved Reserved RW 0 MMD Address 2h, Register 1h – Strap Status 2.1.15:8 Reserved Reserved RO 0000_0000 2.1.
KSZ9031RNX TABLE 4-6: Address MMD REGISTER DESCRIPTIONS (CONTINUED) Mode Note 4-1 Name Description Default 2.2.9 Reserved Reserved RW 0 2.2.8 PME_N1 Output Enable For LED1/PME_N1 (Pin 17), 1 = Enable PME output 0 = Disable PME output This bit works in conjunction with MMD Address 2h, Reg. 10h, Bits [15:14] to define the output for Pin 17. RW 0 2.2.7 Chip PowerDown Override 1 = Override strap-in for chip power-down mode RW Set by MODE[3:0] strapping pin.
KSZ9031RNX TABLE 4-6: Address MMD REGISTER DESCRIPTIONS (CONTINUED) Mode Note 4-1 Name Description Default 2.3.4 NAND Tree Strap-In Status 1 = Strap to NAND Tree mode RO Set by MODE[3:0] strapping pin. See the Strap-In Options KSZ9031RNX section for details. 2.3.3:0 Reserved Reserved RO 0000 MMD Address 2h, Register 4h – RGMII Control Signal Pad Skew 2.4.15:8 Reserved Reserved RW 0000_0000 2.4.7:4 RX_DV Pad Skew RGMII RX_CTL output pad skew control (0.06 ns/ step) RW 0111 2.4.
KSZ9031RNX TABLE 4-6: Address MMD REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default MMD Address 2h, Register 10h – Wake-On-LAN – Control 2.10.15:14 PME Output Select These two bits work in conjunction with MMD Address 2h, Reg. 2h, Bits [8] and [10] for PME_N1 and PME_N2 enable, to define the output for Pins 17 and 38, respectively.
KSZ9031RNX TABLE 4-6: Address MMD REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default MMD Address 2h, Register 12h – Wake-On-LAN – Magic Packet, MAC-DA-1 2.12.15:0 Magic Packet This register stores the middle two bytes of the RW MAC-DA-1 destination MAC address for the magic packet.
KSZ9031RNX TABLE 4-6: Address MMD REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default MMD Address 2h, Register 1Dh – Wake-On-LAN – Customized Packet, Type 0, Mask 1 MMD Address 2h, Register 21h – Wake-On-LAN – Customized Packet, Type 1, Mask 1 MMD Address 2h, Register 25h – Wake-On-LAN – Customized Packet, Type 2, Mask 1 MMD Address 2h, Register 29h – Wake-On-LAN – Customized Packet, Type 3, Mask 1 2.1D.15:0 2.21.15:0 2.25.15:0 2.29.
KSZ9031RNX TABLE 4-6: Address MMD REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default MMD Address 1Ch, Register 23h – EDPD Control 1C.23.15:1 Reserved Reserved RW 0000_0000_0000_00 0 1C.23.0 EDPD Mode Enable Energy-detect power-down mode 1 = Enable 0 = Disable RW 0 Note 4-1 RW = Read/Write; RO = Read Only; WO = Write Only; LH = Latch High. 2016-2017 Microchip Technology Inc.
KSZ9031RNX 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Supply Voltage (VIN) (DVDDL, AVDDL, AVDDL_PLL) ................................................................................................................ –0.5V to +1.8V (AVDDH) ................................................................................................................................................... –0.5V to +5.0V (DVDDH) .................................................................................
KSZ9031RNX 6.0 ELECTRICAL CHARACTERISTICS TA = 25°C. Specification is for packaged product only. TABLE 6-1: SUPPLY CURRENT - CORE/DIGITAL I/O Parameters 1.2V Total of: DVDDL (digital core) + AVDDL (analog core) + AVDDL_PLL (PLL) 1.8V for Digital I/O (RGMII operating @ 1.8V) 2.5V for Digital I/O (RGMII operating @ 2.5V) DS00002117F-page 53 Symbol ICORE IDVDDH_1.8 IDVDDH_2.5 Min. Typ. Max.
KSZ9031RNX TABLE 6-1: SUPPLY CURRENT - CORE/DIGITAL I/O (CONTINUED) Parameters 3.3V for Digital I/O (RGMII operating @ 3.3V) TABLE 6-2: IDVDDH_3.3 Min. Typ. Max. Units — 19.5 — 1000BASE-T link-up (no traffic) — 41.5 — 1000BASE-T full-duplex @ 100% utilization — 13.9 — 100BASE-TX link-up (no traffic) — 17.2 — 100BASE-TX full-duplex @ 100% utilization — 11.5 — — 13.7 — 10BASE-T full-duplex @ 100% utilization — 9.3 — Software power-down mode (Reg. 0.11 = 1) — 2.
KSZ9031RNX TABLE 6-3: CMOS INPUTS Parameters Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current TABLE 6-4: VIH VIL IIHL Min. Typ. Max. 2.0 — — 1.5 — — 1.1 — — — — 1.3 — — 1.0 — — Units Note DVDDH (digital I/O) = 3.3V V DVDDH (digital I/O) = 2.5V DVDDH (digital I/O) = 1.8V DVDDH (digital I/O) = 3.3V V DVDDH (digital I/O) = 2.5V 0.7 DVDDH (digital I/O) = 1.8V µA DVDDH = 3.3V and VIH = 3.3V All digital input pins –2.0 — 2.0 –2.
KSZ9031RNX TABLE 6-6: PULL-UP PINS (Note 6-2) Parameters Internal Pull-Up Resistance (MDC, MDIO, RESET_N pins) Note 6-2 TABLE 6-7: Symbol pu Min. Typ. Max. 13 22 31 16 28 39 Units Note DVDDH (digital I/O) = 3.3V kΩ DVDDH (digital I/O) = 2.5V 26 44 62 Measured with pin input voltage level at one-half DVDDH. DVDDH (digital I/O) = 1.8V 100BASE-TX TRANSMIT (Note 6-3) Parameters Symbol Min. Typ. Max. Units Note Peak Differential Output Voltage VO 0.95 — 1.
KSZ9031RNX 7.0 TIMING DIAGRAMS 7.1 RGMII Timing As the default, after power-up or reset, the KSZ9031RNX RGMII timing conforms to the timing requirements in the RGMII Version 2.0 Specification for internal PHY chip delay. For the transmit path (MAC to KSZ9031RNX), the KSZ9031RNX does not add any delay locally at its GTX_CLK, TX_EN and TXD[3:0] input pins, and expects the GTX_CLK delay to be provided on-chip by the MAC.
KSZ9031RNX FIGURE 7-2: RGMII V2.0 SPEC (MULTIPLEXING AND TIMING DIAGRAM – RGMII-ID (V2.
KSZ9031RNX The RGMII Version 2.0 Specification defines the RGMII data-to-clock skews only for 1000 Mbps operation, which uses both clock edges for sampling the data and control signals at the 125 MHz clock frequency (8 ns period). For 10/100 Mbps operations, the data signals are sampled on the rising clock edge and the control signals are sampled on both clock edges. With slower clock frequencies, 2.
KSZ9031RNX FIGURE 7-3: TABLE 7-2: Timing Parameter AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING PARAMETERS Min. Typ. Max. FLP burst to FLP burst 8 16 24 FLP burst width — 2 — tPW Clock/Data pulse width — 100 — tCTD Clock pulse to data pulse 55.5 64 69.
KSZ9031RNX FIGURE 7-4: TABLE 7-3: MDC/MDIO TIMING MDC/MDIO TIMING PARAMETERS Timing Parameter Description Min. Typ. tP Max. MDC period 120 400 — tMD1 MDIO (PHY input) setup to rising edge of MDC 10 — — tMD2 MDIO (PHY input) hold from rising edge of MDC 10 — — tMD3 MDIO (PHY output) delay from rising edge of MDC 0 — — Units ns The typical MDC clock frequency is 2.5 MHz (400 ns clock period).
KSZ9031RNX FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING NOTE 1 TRANSCEIVER (AVDDH), DIGITAL I/Os (DVDDH) NOTE 3 CORE (DVDDL, AVDDL, AVDDL_PLL) NOTE 2 SUPPLY VOLTAGES tVR tPC tSR RESET_N tCS tCH STRAP-IN VALUE tRC STRAP-IN / OUTPUT PIN Note 1: The recommended power-up sequence is to have the transceiver (AVDDH) and digital I/O (DVDDH) voltages power up before the 1.2V core (DVDDL, AVDDL, AVDDL_PLL) voltage. If the 1.2V core must power up first, the maximum lead time for the 1.
KSZ9031RNX 8.0 RESET CIRCUIT The following are some reset circuit suggestions. Figure 8-1 illustrates the reset circuit for powering up the KSZ9031RNX if reset is triggered by the power supply. FIGURE 8-1: RESET CIRCUIT IF TRIGGERED BY THE POWER SUPPLY DVDDH D1: 1N4148 D1 KSZ9031RNX R 10K RESET_N C 10μF Figure 8-2 illustrates the reset circuit for applications where reset is driven by another device (for example, the CPU or an FPGA).
KSZ9031RNX FIGURE 8-3: RESET CIRCUIT WITH MIC826 VOLTAGE SUPERVISOR DVDDH KSZ9031RNX RESET_N DVDDH MIC826 RESET# Part Number Reset Threshold MIC826TYMT / 3.075V MIC826ZYMT / 2.315V MIC826WYMT / 1.665V DVDDH = 3.3V, 2.5V, or 1.8V 2016-2017 Microchip Technology Inc.
KSZ9031RNX 9.0 REFERENCE CIRCUITS — LED STRAP-IN PINS The pull-up and pull-down reference circuits for the LED2/PHYAD1 and LED1/PHYAD0 strapping pins are shown in Figure 9-1 for 3.3V and 2.5V DVDDH. FIGURE 9-1: REFERENCE CIRCUITS FOR LED STRAPPING PINS DVDDH = 3.3V, 2.5V PULL-UP 10kΩ 220Ω KSZ9031R NX LED PIN DVDDH = 3.3V, 2.5V PULL-DOWN 220Ω KSZ9031R NX LED PIN 1k Ω For 1.
KSZ9031RNX 10.0 REFERENCE CLOCK - CONNECTION AND SELECTION A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ9031RNX. The reference clock is 25 MHz for all operating modes of the KSZ9031RNX. The KSZ9031RNX uses the AVDDH supply, analog 3.3V (or analog 2.5V option for commercial temperature only), for the crystal/clock pins (XI, XO).
KSZ9031RNX 12.0 MAGNETIC - CONNECTION AND SELECTION A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs exceeding FCC requirements. An optional auto-transformer stage following the chokes provides additional commonmode noise and signal attenuation. The KSZ9031RNX design incorporates voltage-mode transmit drivers and on-chip terminations.
KSZ9031RNX TABLE 12-2: COMPATIBLE SINGLE-PORT 10/100/1000 MAGNETICS (CONTINUED) Manufacturer Part Number Auto-Transformer Temperature Range Magnetic + RJ-45 HALO TG1G-S001NZRL No 0°C to 70°C No HALO TG1G-S002NZRL Yes 0°C to 70°C No Pulse H5007NL Yes 0°C to 70°C No Pulse H5062NL Yes 0°C to 70°C No Pulse HX5008NL Yes –40°C to 85°C No Pulse JK0654219NL Yes 0°C to 70°C Yes Pulse JK0-0136NL No 0°C to 70°C Yes TDK TLA-7T101LF No 0°C to 70°C No Wurth/Midcom 000-7093-
KSZ9031RNX 13.0 Note: PACKAGE OUTLINES For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging FIGURE 13-1: 48-LEAD QFN 7 MM X 7 MM PACKAGE WITH 3.5 MM X 3.5 MM EXPOSED PAD AREA 2016-2017 Microchip Technology Inc.
KSZ9031RNX FIGURE 13-2: 48-LEAD QFN 7 MM X 7 MM PACKAGE WITH 5.1 MM X 5.1 MM EXPOSED PAD AREA TITLE 48 LEAD QFN 7x7mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN DRAWING # QFN77-48LD-PL-1 UNIT MM 7.00±0.05 5.10±0.05 Exp.DAP 48 PIN #1 ID CHAMFER 0.35x45° 0.40±0.05 1 2 0.50 Bsc 5.10±0.05 Exp.DAP 7.00±0.05 0.25±0.05 5.50 Ref. Top View Bottom View NOTE: 1, 2, 3 NOTE: 1, 2, 3 0.85±0.05 0.00-0.05 0.253 (REF) Side View NOTE: 1, 2, 3 NOTE: 1. MAX PACKAGE WARPAGE IS 0.05mm. 2.
KSZ9031RNX FIGURE 13-3: 48-LEAD QFN 7 MM X 7 MM PACKAGE WITH 5.1 MM X 5.1 MM EXPOSED PAD AREA RECOMMENDED LAND PATTERN POD-Land Pattern drawing #: QFN77-48LD-PL-1-C 2016-2017 Microchip Technology Inc.
KSZ9031RNX FIGURE 13-4: DS00002117F-page 72 48-LEAD VQFN 7 MM X 7 MM PACKAGE (WETTABLE FLANK) WITH 5.05 MM X 5.05 MM EXPOSED PAD AREA 2016-2017 Microchip Technology Inc.
KSZ9031RNX FIGURE 13-5: 48-LEAD VQFN 7 MM X 7 MM PACKAGE (WETTABLE FLANK) WITH 5.05 MM X 5.05 MM EXPOSED PAD AREA RECOMMENDED LAND PATTERN 2016-2017 Microchip Technology Inc.
KSZ9031RNX APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision Section/Figure/Entry Correction DS00002117F (06-02-17) Table 2-1, "Signals KSZ9031RNX" Added the following note to pin description for pin 43: Note: This pin should never be driven externally. DS00002117E (05-26-17) Product Identification System - Added “wettable flank lead frame” after VQFN for automotive grade ordering examples e through l.
KSZ9031RNX TABLE A-1: REVISION HISTORY (CONTINUED) Revision DS00002117D (01-05-17) Section/Figure/Entry Correction All Sales listing and cover pages updated. Minor text changes throughout. Features on page 1 Updated info for AEC-Q100 Qualified for Automotive Applications. Target Applications on page 1 Added Automotive In-Vehicle Networking. Section 5.2, "Operating Ratings**," on page 52 Updated maximum operating voltage for (DVDDL, AVDDL, AVDDL_PLL).
KSZ9031RNX THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
KSZ9031RNX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X XX X Interface Package Temp.
KSZ9031RNX Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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