Datasheet

Micrel, Inc. KS8999
January 2005
48
KS8999
Figure 21. Recommended Circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the KS8999 device. The reset out
from CPU/FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage
earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same
time.