Datasheet

Micrel, Inc. KS8999
January 2005
28
KS8999
Optional CPU Interface
Instead of using an EEPROM to program the KS8999, one can use an external processor. To utilize this feature, the
CFGMODE pin (only available on the 208 pin package) needs to pulled low. This makes the KS8999 serial and clock
interface into a slave rather than a master. In this mode, clock and data are sourced from the processor.
Due to timing constraints, the maximum clock speed that the processor can generate is 8MHz. Data timing is
referenced to the rising edge of the clock and are 10ns for setup and 60ns for hold. The processor needs to supply
the exact number of clock cycles and data bits to program the KS8999 properly. KS8999 won’t start until all of the
registers are programmed. Bits are loaded from high order (bit 7) to low order (bit 0) starting with register 0 and
finishing with register 53.
Register 0: Skip clock on first bit 7 SCL clock cycle: 7
Register 1 to Register 53: provide clock on bit 7 to bit 0 SCL clock cycle: 424
Total SCL clock cycle: 431