Datasheet

Micrel, Inc. KS8999

January 2005

KS8999

The table below briefly summarizes VLAN features. For more detailed settings see the EEPROM register description.

4-12 2 Port Insert VLAN Tags: If specified, will add VLAN tags to frames without existing tags

4-12 1 Port Strip VLAN Tags: If specified, will remove VLAN tags from frames if they exist

2 0 Global VLAN Enforcement: Allows unicast frames to adhere or ignore the VLAN configuration

13-21 7-0 Port VLAN Mask Registers: Allows configuration of individual VLAN grouping.

22-39 7-0 Port VLAN Tag Insertion Values: Specifies the VLAN tag to be inserted if enabled (see

above)

Table 4. VLAN Control

Station MAC Address (control frames only)

The MAC source address can be programmed as used in flow control frames. The table below briefly summarizes

this programmable feature.

48-53 7-0 Global Station MAC Address: Used as source address for MAC control frames as used in full

duplex flow control mechanisms.

Table 5. Misc. Control

EEPROM Operation

The EEPROM interface utilizes 2 pins that provide a clock and a serial data path. As part of the initialization

sequence, the KS8999 reads the contents of the EEPROM and loads the values into the appropriate registers. Note

that the first two bytes in the EEPROM must be “55” and “99” respectively for the loading to occur properly. If these

first two values are not correct, all other data will be ignored.

Data start and stop conditions are signaled on the data line as a state transition during clock high time. A high to low

transition indicates start of data and a low to high transition indicates a stop condition. The actual data that traverses

the serial line changes during the clock low time.

The KS8999 EEPROM interface is compatible with the Atmel AT24C01A part. Address A0, A1 and A2 are fixed to

000. Further timing and data sequences can be found in the Atmel AT24C01A specification.