Datasheet

Micrel, Inc. KS8999
January 2005
17
KS8999
Group I/O Names Active Status Description
LED[7][3]
Programs flow control D = No flow control, F/U = Flow control enabled
(default)
LED[7][2]
Programs broadcast storm protection. D = 5% broadcast frames allowed, F/U
= Unlimited broadcast frames (default)
LED[7][1]
Programs buffer sharing feature. D = Equal amount of buffers per port (113
buffers), F/U = Share buffers up to 512 buffers on a single port (default)
LED[7][0] Reserved – use float configuration
LED[8][3]
Programs address aging.
D = Aging disabled, F/U = Enable 5 minute aging (default)
LED[8][2]
Programs frame length enforcement. D = Max length for VLAN is 1522 bytes
and without VLAN is 1518 bytes F/U = Max length is 1536 bytes (default)
LED[8][1] Reserved
LED[8][0]
Programs half-duplex back pressure. D = No half-duplex back pressure,
F/U = Half-duplex back pressure enabled (default)
MRXD[3] Programs port 9 speed D = 10Mbps, F/U = 100Mbps (default)
MRXD[2] Programs port 9 duplex D = Half-duplex, F/U = Full duplex (default)
MRXD[1] Programs port 9 flow control D = Flow control, F/U = No flow control (default)
MRXD[0] D = reserved, F/U = normal operation (default)
CTRL EN1P H
Enable 802.1p for all ports –this enables QoS based on the priority field in the
layer 2 header.
0 = 802.1p selected by port in EEPROM
1 = Use 802.1p priority field unless disabled in EEPROM
Note: This is also controlled by the EEPROM registers (registers 4-12 bit 4).
The values in the EEPROM supersede this pin. Also, if the priority selection is
unaltered in the EEPROM registers (register 3 bits 0-7) then values above 3
are considered high priority and less than 4 are low priority.
MIIS[1:0] H MII mode selection –allows the MII to run in the following modes
MIIS
1 0
Operating mode
0 0
0 1
1 0
1 1
Disable MII interface
Reverse MII
Forward MII
7 wire mode (SNI)
PRSV H Priority buffer reserve –reserves 6KB of buffer space for the priority traffic if
enabled. 0 = No priority reserve 1 = Reserve 6KB for priority traffic
Note: This is also controlled by the EEPROM registers (register 2 bit 1). The
value in the EEPROM supersedes this pin.
CFGMODE H Selects between EEPROM or processor for programming interface.
0 = Processor interface
1 = EEPROM interface or not programmed on this interface (SCL / SDA not
used)
X1 Clock External crystal or clock input
X2 Clock Used when other polarity of crystal is needed. This is unused for a normal
clock input.
SCL Clock Clock for EEPROM
SDA I/O Serial data for EEPROM
RST# L System reset
TEST TESTEN H Factory test input –tie low for normal operation
SCANEN H Factory test input –tie low for normal operation
MUX[1:2] H Factory test input –leave open for normal operation
AOUT H Factory test output –leave open for normal operation