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KS8995MA/FQ

Integrated 5-Port 10/100 Managed Switch

Rev. 3.0

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

October 2011

M9999-102611-3.0

General Description

The KS8995MA/FQ is a highly-integrated Layer 2

managed switch with optimized bill of materials (BOM)

cost for low port count, cost-sensitive 10/100Mbps switch

systems with both copper and optic fiber media.

It also provides an extensive feature set such as tag/port-

based VLAN, quality of service (QoS) priority,

management, MIB counters, dual MII interfaces and CPU

control/data interfaces to effectively address both current

and emerging fast Ethernet applications.

The KS8995MA/FQ contains five 10/100 transceivers with

patented mixed-signal low-power technology, five media

access control (MAC) units, a high-speed non-blocking

switch fabric, a dedicated address lookup engine, and an

on-chip frame buffer memory.

All PHY units support 10BASE-T and 100BASE-TX.

In addition, two of the PHY units support 100BASE-FX on

ports 4 and 5 for KSZ8995MA, two of the PHY units

support 100BASE-FX on ports 3 and 4 for KSZ8995FQ.

Datasheets and support documentation can be found on

Micrel’s web site at: www.micrel.com.

Functional Diagram

Summary of content (89 pages)

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KS8995MA/FQ Integrated 5-Port 10/100 Managed Switch Rev. 3.0 General Description The KS8995MA/FQ is a highly-integrated Layer 2 managed switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems with both copper and optic fiber media.
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Micrel, Inc. KS8995MA/FQ Features • Integrated switch with five MACs and five fast Ethernet transceivers fully-compliant to IEEE 802.3u standard • Shared memory based switch fabric with fully nonblocking configuration • 1.4Gbps high-performance memory bandwidth • 10BASE-T, 100BASE-TX, and 100BASE-FX modes • Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII). • IEEE 802.
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Micrel, Inc. KS8995MA/FQ Ordering Information Part Number Temperature Range Package 0°C to +70°C 128-Pin PQFP KSZ8995FQ 0°C to +70°C 128-Pin PQFP KSZ8995MAI −40°C to +85°C 128-Pin PQFP KSZ8995FQI −40°C to +85°C 128-Pin PQFP Standard Pb (lead)-Free KS8995MA KSZ8995MA KS8995FQ KS8995MAI KS8995FQI Revision History Revision Date 2.0 10/10/03 Created. 2.1 10/30/03 Editorial changes on electrical characteristics. 2.
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Micrel, Inc. KS8995MA/FQ Contents System Level Applications................................................................................................................................................. 11 Pin Configuration ................................................................................................................................................................ 13 Pin Description − By Number.............................................................................................
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Micrel, Inc. KS8995MA/FQ Configuration Interface ..................................................................................................................................................... 41 MII Management Interface (MIIM) .................................................................................................................................... 45 Register Description .......................................................................................................................
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Micrel, Inc. KS8995MA/FQ Register 52 (0x34): Port 3 Control 4 ................................................................................................................................. 55 Register 68 (0x44): Port 4 Control 4 ................................................................................................................................. 55 Register 84 (0x54): Port 5 Control 4 ............................................................................................................
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Micrel, Inc. KS8995MA/FQ Register 93 (0x5D): Port 5 Control 13 .............................................................................................................................. 59 Register 30 (0x1E): Port 1 Status 0 .................................................................................................................................. 60 Register 46 (0x2E): Port 2 Status 0 ...............................................................................................................
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Micrel, Inc. KS8995MA/FQ Register 121 (0x79): Digital Testing Status 0 ................................................................................................................... 65 Register 122 (0x7A): Digital Testing Status 1 ................................................................................................................... 65 Register 123 (0x7B): Digital Testing Control 0 ............................................................................................................
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Micrel, Inc. KS8995MA/FQ List of Figures Figure 1. Broadband Gateway ............................................................................................................................................ 11 Figure 2. Integrated Broadband Router .............................................................................................................................. 11 Figure 3. Standalone Switch .....................................................................................................
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Micrel, Inc. KS8995MA/FQ List of Tables Table 1. MII − P5 Signals (PHY Mode) ............................................................................................................................... 34 Table 2. MII − SW Signals................................................................................................................................................... 35 Table 3. SNI Signals .........................................................................................................
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Micrel, Inc. KS8995MA/FQ System Level Applications Figure 1. Broadband Gateway Figure 2. Integrated Broadband Router October 2011 11 M9999-102611-3.
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Micrel, Inc. KS8995MA/FQ System Level Applications (Continued) Figure 3. Standalone Switch Figure 4. Using KS8995FQ for Dual Media Converter or Fiber Daisy Chain Connection October 2011 12 M9999-102611-3.
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Micrel, Inc. KS8995MA/FQ Pin Configuration 128-Pin PQFP October 2011 13 M9999-102611-3.
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Micrel, Inc. KS8995MA/FQ Pin Description − By Number Pin Number Pin Name Type(1) Port Pin Function(2) 1 MDI-XDIS lpd 1−5 Disable auto MDI/MDI-X. PD (default) = normal operation. PU = disable auto MDI/MDI-X on all ports. 2 GNDA GND 3 VDDAR P Notes: 1. 2. Analog ground. 1.8V analog VDD. 4 RXP1 I 1 Physical receive signal + (differential). 5 RXM1 I 1 Physical receive signal – (differential). 6 GNDA GND 7 TXP1 O 1 Physical transmit signal + (differential).
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Micrel, Inc. KS8995MA/FQ Pin Description − By Numbers (Continued) Pin Number Pin Name Type(1) 31 VDDAR P 32 RXP5 I 5 Physical receive signal + (differential). 5 Physical receive signal – (differential). Port Pin Function 1.8V analog VDD. 33 RXM5 I 34 GNDA GND 35 TXP5 O 5 Physical transmit signal + (differential). 36 TXM5 O 5 Physical transmit signal – (differential).
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Micrel, Inc. KS8995MA/FQ Pin Description − By Numbers (Continued) Pin Number Pin Name Type(1) 61 PMRXDV Ipd/O Notes: 1. 2. Port Pin Function(2) 5 PHY[5] MII receive data valid. 5 PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. 5 PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. 5 PHY[5] MII receive bit 1.
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Micrel, Inc. KS8995MA/FQ Pin Description − By Numbers (Continued) Pin Number Pin Name Type(1) 82 SMRXD1 Ipd/O Port Pin Function(2) Switch MII receive bit 1. Strap option: PD (default) = Switch MII in 100Mbps mode; PU = Switch MII in 10Mbps mode. Switch MII receive bit 0; Strap option: LED mode; PD (default) = mode 0; PU = mode 1. See “Register 11”. Mode 0, link at: 100/Full LEDx[2,1,0]=0,0,0 100/Half LEDx[2,1,0]=0,1,0 10/Full LEDx[2,1,0]=0,0,1 10/Half LEDx[2,1,0]=0,1,1 Mode 1, link at 83 2.
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Micrel, Inc. KS8995MA/FQ Pin Description − By Numbers (Continued) Pin Number Pin Name Type(1) Port 92 LED5-0 Ipu/O 5 LED indicator 0. 93 LED4-2 Ipu/O 4 LED indicator 2. 94 LED4-1 Ipu/O 4 LED indicator 1. 95 LED4-0 Ipu/O 4 LED indicator 0. 96 LED3-2 Ipu/O 3 LED indicator 2. 97 LED3-1 Ipu/O 3 LED indicator 1. 98 LED3-0 Ipu/O 3 99 GNDD GND 100 VDDIO P 101 LED2-2 Ipu/O 2 LED indicator 2. 102 LED2-1 Ipu/O 2 LED indicator 1.
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Micrel, Inc. KS8995MA/FQ Pin Description − By Numbers (Continued) Pin Number Pin Name Type(1) 114 PS0 Ipd Serial bus configuration pin. See “Pin 113.” 115 RST_N Ipu Reset the KS8995MA/FQ. Active low. 116 GNDD GND 117 VDDC P 118 TESTEN Ipd NC for normal operation. Factory test pin. 119 SCANEN Ipd NC for normal operation. Factory test pin. 120 NC NC No connect. 121 X1 I 122 X2 O 25MHz crystal clock connection. 123 VDDAP P 1.8V analog VDD for PLL.
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Micrel, Inc. KS8995MA/FQ Pin Description − By Name Pin Number Pin Name Type(1) Port 39 FXSD4 I 4 3/5 Note: 1. Pin Function Fiber signal detect/Factory test pin. 38 FXSD3/FXSD5 I 124 GNDA GND Fiber signal detect/Factory test pin for FQ port 3 or MA port 5 Analog ground. 42 GNDA GND Analog ground. 44 GNDA GND Analog ground. 2 GNDA GND Analog ground. 16 GNDA GND Analog ground. 30 GNDA GND Analog ground. 6 GNDA GND Analog ground. 12 GNDA GND Analog ground.
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Micrel, Inc. KS8995MA/FQ Pin Description − By Name (Continued) Pin Number Pin Name Type(1) Port Pin Function(2) 97 LED3-1 Ipu/O 3 LED indicator 1. 96 LED3-2 Ipu/O 3 LED indicator 2. 95 LED4-0 Ipu/O 4 LED indicator 0. 94 LED4-1 Ipu/O 4 LED indicator 1. 93 LED4-2 Ipu/O 4 LED indicator 2. 92 LED5-0 Ipu/O 5 LED indicator 0. 91 LED5-1 Ipu/O 5 LED indicator 1. Strap option: PU (default) = enable PHY MII I/F PD: tristate all PHY MII output. See “Pin 86 SCONF1.
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Micrel, Inc. KS8995MA/FQ Pin Description − By Name Pin Number Pin Name Type(1) Port 57 PMTXC O 5 PHY[5] MII transmit clock. PHY mode MII. 55 PMTXD0 Ipd 5 PHY[5] MII transmit bit 0. 54 PMTXD1 Ipd 5 PHY[5] MII transmit bit 1. 53 PMTXD2 Ipd 5 PHY[5] MII transmit bit 2. 52 PMTXD3 Ipd 5 PHY[5] MII transmit bit 3. 51 PMTXEN Ipd 5 PHY[5] MII transmit enable. 5 PHY[5] MII transmit error. Note: 1. Pin Function 56 PMTXER Ipd 114 PS0 Ipd Serial bus configuration pin.
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Micrel, Inc. KS8995MA/FQ Pin Description − By Name Pin Number Pin Name Type(1) 86 SCONF1 Ipd Port Pin Function(2) Dual MII configuration pin. For the Switch MII, KSZ8995MA supports both MAC mode and PHY mode, KSZ8995FQ supports PHY mode only.
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Micrel, Inc. KS8995MA/FQ Pin Description − By Name Pin Number Pin Name Type(1) Port 110 SPIC/SCL I/O All (1) Input clock up to 5MHz in SPI slave mode; (2) output clock at 61kHz in I2C master mode. See “Pin 113.” 111 SSPID/SDA I/O All (1) Serial data input in SPI slave mode; (2) serial data input/output in I2C master mode. See “Pin 113.” 109 SPIQ Otri All (1) SPI serial data output in SPI slave mode; (2) output clock at 61kHz in I2C master mode. See “Pin 113.
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Micrel, Inc. KS8995MA/FQ Pin Description − By Name Pin Number Pin Name Type(1) 89 VDDC P 117 VDDC P 1.8V digital core VDD. 59 VDDIO P 3.3V digital VDD for digital I/O circuitry. 77 VDDIO P 3.3V digital VDD for digital I/O circuitry. 100 VDDIO P 3.3V digital VDD for digital I/O circuitry. 121 X1 I 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should be ±50ppm. 122 X2 O 25MHz crystal clock connection. Note: 1. Port Pin Function 1.
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Micrel, Inc. KS8995MA/FQ Introduction The KS8995MA/FQ contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode is as a five-port integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this mode, access to the fifth MAC is provided through a media independent interface (MII).
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Micrel, Inc. KS8995MA/FQ Scrambler/De-Scrambler (100BASE-TX Only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter.
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Micrel, Inc. KS8995MA/FQ Auto-Negotiation The KS8995MA/FQ conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In auto-negotiation the link partners advertise capabilities across the link to each other.
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Micrel, Inc. KS8995MA/FQ Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KS8995MA/FQ is guaranteed to learn 1K addresses and distinguishes itself from a hashbased look-up table, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn.
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Micrel, Inc. KS8995MA/FQ Media Access Controller (MAC) Operation The KS8995MA/FQ strictly abides by IEEE 802.3 standards to maximize compatibility. Inter-Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN. Backoff Algorithm The KS8995MA/FQ implements the IEEE Std. 802.
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Micrel, Inc. KS8995MA/FQ Figure 6. DA Look-Up Flowchart − 1 October 2011 31 M9999-102611-3.
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Micrel, Inc. KS8995MA/FQ Figure 7. DA Resolution Flowchart − Stage 2 October 2011 32 M9999-102611-3.
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Micrel, Inc. KS8995MA/FQ Half-Duplex Back Pressure The KS8995MA/FQ also provides a half-duplex back-pressure option (Note: this is not in IEEE 802.3 standards). The activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required, the KS8995MA/FQ sends preambles to defer the other station's transmission (carrier sense deference). To avoid jabber and excessive deference as defined in IEEE 802.
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Micrel, Inc. KS8995MA/FQ SNI Interface Operation The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing. This interface can be directly connected to these types of devices. The signals are divided into two groups, one for transmission and the other for reception. The signals involved are described in Table 3.
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Micrel, Inc. KS8995MA/FQ Learning state: only packets to and from the processor are forwarded. Learning is enabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.” Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor.
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Micrel, Inc. Ingress Tag Field (0x810+ Port Mask) (0x810+ Port Mask) (0x810+ Port Mask) (0x810+ Port Mask) Not Tagged KS8995MA/FQ Tx Port “Tag Insertion” 0 Tx Port “Tag Removal” 0 0 1 1 0 1 1 Don’t Care Don’t Care Egress Action to Tag Field • Modify tag field to 0x8100. • Recalculate CRC. • No change to TCI if not null VID. • Replace VID with ingress (port 5) port VID if null VID. • (STPID + TCI) will be removed. • Padding to 64 bytes if necessary. • Recalculate CRC.
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Micrel, Inc. KS8995MA/FQ IGMP Support There are two parts involved to support IGMP in Layer 2. The first part is “IGMP” snooping. The switch will trap IGMP packets and forward them only to the processor port. The IGMP packets are identified as IP packets (either Ethernet IP packets or IEEE 802.3 SNAP IP packets) AND IP version = 0x4 AND protocol number = 0x2. The second part is “multicast address insertion” in the static MAC table.
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Micrel, Inc. KS8995MA/FQ VLAN Support KS8995MA/FQ supports 16 active VLANs out of 4096 possible VLANs specified in IEEE 802.1q. KS8995MA/FQ provides a 16-entry VLAN table, which converts VID (12 bits) to FID (4 bits) for address look-up. If a non-tagged or null-VID-tagged packet is received, the ingress port VID is used for look-up. In the VLAN mode, the look-up process starts with VLAN table look-up to determine whether the VID is valid.
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Micrel, Inc. KS8995MA/FQ Configuration Interface The KS8995MA/FQ can function as a managed switch or unmanaged switch. If no EEPROM or micro-controller exists, the KS8995MA/FQ will operate from its default setting. Some default settings are configured via strap in options as indicated in the following tables. Pin # Pin Name PU/PD(1) 1 MDI-XDIS Ipd 45 MUX1 NC 46 MUX2 NC Description(1) Disable auto MDI/MDI-X. PD = (default) = normal operation PU = disable auto MDI/MDI-X on all ports.
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Micrel, Inc. Pin # KS8995MA/FQ Pin Name PU/PD(1) Description(1) Dual MII configuration pin. For the Switch MII, KSZ8995MA supports both MAC mode and PHY mode, KSZ8995FQ supports PHY mode only.
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Micrel, Inc. KS8995MA/FQ I2C Master Serial Bus Configuration If a 2-wire EEPROM exists, the KS8995MA/FQ can perform more advanced features like broadcast storm protection and rate control. The EEPROM should have the entire valid configuration data from Register 0 to Register 109 defined in the “Memory Map,” except the status registers. After reset, the KS8995MA/FQ will start to read all 110 registers sequentially from the EEPROM.
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Micrel, Inc. KS8995MA/FQ To use the KS8995MA/FQ SPI: 1. At the board level, connect KS8995MA/FQ pins as follows: KS8995MA/FQ Pin Number KS8995MA/FQ Signal Name Microprocessor Signal Description 112 SPIS_N SPI Slave Select 110 SPIC SPI Clock 111 SPID Master Out Slave Input 109 SPIQ Master In Slave Output Table 9. SPI Connections 2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “10” to set the serial configuration to SPI slave mode. 3.
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Micrel, Inc. KS8995MA/FQ SPIS_N SPIC SPID X 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 SPIQ WRITE COMMAND WRITE ADDRESS Byte 1 SPIS_N SPIC SPID D7 D6 D5 D4 D4 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D7 D0 D6 D5 D4 D3 SPIQ Byte 2 Byte 3 ... Byte N Figure 11.
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Micrel, Inc. KS8995MA/FQ Global Registers Address Name Description Mode Default Family ID Chip Family. RO 0x95 Name Description Mode Default RO 0x0 Register 0 (0x00): Chip ID0 7−0 Address Register 1 (0x01): Chip ID1 / Start Switch 7−4 3−1 0 Chip ID Revision ID Start Switch 0x0 is assigned to M series. (95MA) Revision ID RO 1, start the chip when external pins (PS1, PS0) = (1,0) or (0,1).
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Micrel, Inc. KS8995MA/FQ Global Registers (Continued) Address Name Description Mode Default R/W 0 R/W 0 Register 2 (0x02): Global Control 0 1 UNH Mode 1, the switch will drop packets with 0x8808 in T/L filed, or DA=01-80C2-00-00-01. 0, the switch will drop packets qualified as “flow control” packets. 0 Address Link Change Age 1, link change from “link” to “no link” will cause fast aging (<800µs) to age address table faster.
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Micrel, Inc. KS8995MA/FQ Global Registers (Continued) Address 1 0 Address Name Description Fast Age Enable 1 = Turn on fast age (800µs). Mode Aggressive Back Off Enable 1 = Enable more aggressive back-off algorithm in half duplex mode to enhance performance. This is not an IEEE standard. Name Description Default R/W 0 R/W Pin PMRXD0 strap option. Pull-down (0): Disable aggressive back off. Pullup (1): Aggressive back off. Note: PMRXD0 has internal pull down.
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Micrel, Inc. KS8995MA/FQ Global Registers (Continued) Address Name Description Mode Default R/W Pin PMRXER strap option. Pull-down (0): 1518/1522 byte packets. Pull-up (1): 1536 byte packets. Note: PMRXER has internal pull-down. R/W 0 Mode Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 00 R/W 0 R/W 0 Register 4 (0x04): Global Control 2 1, will accept packet sizes up to 1536 bytes (inclusive).
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Micrel, Inc. KS8995MA/FQ Global Registers (Continued) Address Name Description Mode Default R/W 0 R/W Pin SMRXD2 strap option. Pull-down (0): Full-duplex mode. Pull-up (1): Halfduplex mode. Note: SMRXD2 has internal pulldown. R/W Pin SMRXD3 strap option. Pull-down (0): disable flow control. Pull-up(1): enable flow control. Note: SMRXD3 has internal pulldown. R/W Pin SMRXD1 strap option. Pull-down (0): Enable 100Mbps. Pull-up (1): Enable 10Mpbs.Note: SMRXD1 has internal pulldown.
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Micrel, Inc. KS8995MA/FQ Global Registers (Continued) Address Name Description Mode Default R/W 0x24 Mode Default Register 10 (0x0A): Global Control 8 7−0 Address Factory Testing Reserved Name Description Register 11 (0x0B): Global Control 9 7−5 Reserved N/A RO 0 4 Reserved N/A RO 0 3 Reserved N/A RO 0 2 Factory Setting Reserved R/W 0 0 = led mode 0. 1 = led mode 1.
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Micrel, Inc. KS8995MA/FQ Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated.
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Micrel, Inc. KS8995MA/FQ Port Registers (Continued) Address Name Description Mode Default Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Register 65 (0x41): Port 4 Control 1 Register 81 (0x51): Port 5 Control 1 7 Sniffer Port 1, port is designated as sniffer port and will transmit packets that are monitored. 0, port is a normal port.
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Micrel, Inc. KS8995MA/FQ Port Registers (Continued) Address Name Description Mode Default Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Register 66 (0x42): Port 4 Control 2 Register 82 (0x52): Port 5 Control 2 3 Back Pressure Enable 1, enable port half-duplex back pressure. 0, disable port half-duplex back pressure. R/W Pin PMRXD2 strap option. Pull-down (0): disable back pressure. Pull-up(1): enable back pressure.
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Micrel, Inc. KS8995MA/FQ Port Registers (Continued) Address Name Description Mode Default Register 27 (0x1B): Port 1 Control 11 Register 43 (0x2B): Port 2 Control 11 Register 59 (0x3B): Port 3 Control 11 Register 75 (0x4B): Port 4 Control 11 Register 91 (0x5B): Port 5 Control 11 High Priority Receive Rate Flow Control Enable 1, flow control may be asserted if the port’s high priority receive rate is exceeded. To use this, differential receive rate control must be on.
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Micrel, Inc. KS8995MA/FQ Port Registers (Continued) Address Name Description Mode Default Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Port 3 Control 12 Register 76 (0x4C): Port 4 Control 12 Register 92 (0x5C): Port 5 Control 12 3 Advertised 100BT FullDuplex Capability 1, advertise 100BT full-duplex capability. 0, suppress 100BT full-duplex capability from transmission to link partner.
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Micrel, Inc. KS8995MA/FQ Port Registers (Continued) Address Name Description Mode Default Register 30 (0x1E): Port 1 Status 0 Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Port 3 Status 0 Register 78 (0x4E): Port 4 Status 0 Register 94 (0x5E): Port 5 Status 0 7 MDIX Status 1, MDI-X. 0, MDI. RO 0 6 AN Done 1, AN done. 0, AN not done. RO 0 5 Link Good 1, link good. 0, link not good. RO 0 4 Partner Flow Control Capability 1, link partner flow control capable.
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Micrel, Inc. KS8995MA/FQ Advanced Control Registers The IPv4 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used to determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is compared against the corresponding bit in the DSCP register.
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Micrel, Inc. KS8995MA/FQ Advanced Control Registers (Continued) Address Name Description Mode Default R/W 00000000 Mode Default R/W 00000000 Register 102 (0x66): TOS Priority Control Register 6 7−0 Address DSCP[15:8] Name Description Register 103 (0x67): TOS Priority Control Register 7 7−0 DSCP[7:0] Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in MAC pause control frames.
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Micrel, Inc. KS8995MA/FQ Advanced Control Registers (Continued) Address Name Description Mode Default R/W 0xff Register 109 (0X6D): MAC Address Register 5 7−0 MACA[7:0] Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or the MIB counters.
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Micrel, Inc. KS8995MA/FQ Advanced Control Registers (Continued) Address Name Description Mode Default R/W 00000 Mode Default R/W 00000000 Mode Default R/W 00000000 Mode Default R/W 00000000 Mode Default R/W 00000000 Mode Default R/W 00000000 Mode Default R/W 00000000 Mode Default R/W 00000000 Register 112 (0x70): Indirect Data Register 8 68 − 64 Address Indirect Data Bit 68-64 of indirect data.
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Micrel, Inc. KS8995MA/FQ Advanced Control Registers (Continued) Address Name Description Mode Default R/W 00000000 Register 120 (0x78): Indirect Data Register 0 7−0 Indirect Data Bit 7-0 of indirect data. Do not write or read to/from Registers 121 to 127. Doing so may prevent proper operation. Micrel internal testing only. Address Name Description Mode Default RO 0x0 Mode Default RO 0x0 Mode Default R/W 0x0 Mode Default R/W 0x0 Mode Default R/W 0x0 Mode Default Reserved.
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Micrel, Inc. KS8995MA/FQ Static MAC Address KS8995MA/FQ has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is searched for aging, migration, and learning purposes. The static DA look-up result will have precedence over the dynamic DA look-up result. If there are DA matches in both tables, the result from the static table will be used.
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Micrel, Inc. KS8995MA/FQ VLAN Address The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 Bit 7 = 1), this table is used to retrieve VLAN information that is associated with the ingress packet. The information includes FID (filter ID), VID (VLAN ID), and VLAN membership described below: Address Name Description Mode Default R/W 1 R/W 11111 R/W 0 R/W 1 Format of Static VLAN Table (16 entries) 21 Valid 1, the entry is valid. 0, entry is invalid.
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Micrel, Inc. KS8995MA/FQ Dynamic MAC Address The table below is read only; the contents are managed by the KS8995MA/FQ only. Address Name Description Mode Default RO 1 RO 0 Format of Dynamic MAC Address Table (1K entries) 68 MAC Empty 1, there is no valid entry in the table. 0, there are valid entries in the table. Indicates how many valid entries in the table.
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Micrel, Inc. KS8995MA/FQ MIB Counters The MIB counters are provided on per-port basis. The indirect memory is as detailed in the following table(s). Offset Counter Name Description 0x0 RxLoPriorityByte Rx lo-priority (default) octet count including bad packets. 0x1 RxHiPriorityByte Rx hi-priority octet count including bad packets. 0x2 RxUndersizePkt Rx undersize packets w/good CRC. 0x3 RxFragments Rx fragment packets w/bad CRC, symbol errors or alignment errors.
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Micrel, Inc. Address KS8995MA/FQ Name Description Mode Default RO 0 RO 0 RO 0 Mode Default For port 2, the base is 0x20, same offset definition (0x20-0x3f) For port 3, the base is 0x40, same offset definition (0x40-0x5f) For port 4, the base is 0x60, same offset definition (0x60-0x7f) For port 5, the base is 0x80, same offset definition (0x80-0x9f) Format of Per Port MIB Counters (16 entries) 31 Overflow 30 Count Valid 1, Counter overflow. 0, No Counter overflow. 1, Counter value is valid.
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Micrel, Inc. KS8995MA/FQ MIIM Registers All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for port 1, “0x2” for port 2, “0x3” for port 3, “0x4” for port 4, and “0x5” for port 5. The “REGAD” supported are 0, 1, 2, 3, 4, 5.
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Micrel, Inc. KS8995MA/FQ MIIM Registers (Continued) Address Name Description Mode Default RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 Register 1: MII Status 15 T4 Capable 14 100 Full Capable 13 100 Half Capable 12 10 Full Capable 11 10 Half Capable 10 − 7 0, Not 100 BASET4 capable. 1, 100BASE-TX full-duplex capable. 0, Not capable of 100BASE-TX full-duplex. 1, 100BASE-TX half-duplex capable. 0, Not 100BASE-TX half-duplex capable.
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Micrel, Inc. KS8995MA/FQ MIIM Registers (Continued) Address Name Description Mode Default RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 802.3 RO 00001 Register 4: Advertisement Ability 15 Next Page 14 Reserved 13 Remote fault 12 − 11 Not supported. Reserved 10 Pause 9 Reserved 8 Adv 100 Full 7 Adv 100 Half 6 Adv 10 Full 5 Adv 10 Half 4−0 Not supported. Selector Field 1, Advertise pause ability. 0, Do not advertise pause ability.
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Micrel, Inc. KS8995MA/FQ Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VDDR, VDDAP, VDDC). ............................... −0.5V to +2.4V (VDDAT, VDDIO) ......................................... −0.5V to +4.0V Input Voltage ................................................ −0.5V to +4.0V Output Voltage ............................................. −0.5V to +4.0V Lead Temperature (soldering, 10s) ............................ 260°C Storage Temperature (Ts) .........................
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Micrel, Inc. KS8995MA/FQ Electrical Characteristics(4, 5) (Continued) Symbol Parameter Condition Min. Typ. Max. Units 100BASE-TX Transmit (measured differentially after 1:1 transformer) VO Peak Differential Output Voltage 100Ω termination on the differential output VIMB Output Voltage Imbalance 100Ω termination on the differential output tr tt 0.95 Rise/fall Time 3 Rise/fall Time Imbalance 0 1.00 Duty Cycle Distortion Overshoot VSET Reference Voltage of ISET Output Jitters 1.
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Micrel, Inc. KS8995MA/FQ Timing Diagrams Figure 13. EEPROM Interface Input Receive Timing Diagram Figure 14. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter Min. Typ. Max. tCYC1 Clock Cycle tS1 Set-Up Time 20 ns tH1 Hold Time 20 ns tOV1 Output Valid 16384 4096 4112 Units ns 4128 ns Table 10. EEPROM Timing Parameters October 2011 79 M9999-102611-3.
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Micrel, Inc. KS8995MA/FQ Timing Diagrams (Continued) Figure 15. SNI Input Timing Figure 16. SNI Output Timing Symbol Parameter Min. Typ. Max. tCYC2 Clock Cycle tS2 Set-Up Time 10 ns tH2 Hold Time 0 ns tO2 Output Valid 0 100 3 Units ns 6 ns Table 11. SNI Timing Parameters October 2011 80 M9999-102611-3.
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Micrel, Inc. KS8995MA/FQ Timing Diagrams (Continued) Figure 17. MAC Mode MII Timing − Data Received from MII Figure 18. MAC Mode MII Timing − Data Transmitted from MII 10Base-T/100Base-TX Symbol Parameter tCYC3 Clock Cycle tS3 Set-Up Time 10 ns tH3 Hold Time 5 ns tOV3 Output Valid 3 Min. Typ. Max. 400/40 9 Units ns 25 ns Table 12. MAC Mode MII Timing Parameters October 2011 81 M9999-102611-3.
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Micrel, Inc. KS8995MA/FQ Timing Diagrams (Continued) Figure 19. PHY Mode MII Timing − Data Received from MII Figure 20. PHY Mode MII Timing − Data Transmitted from MII 10BaseT/100BaseT Symbol Parameter tCYC4 Clock Cycle tS4 Set-Up Time 10 ns tH4 Hold Time 0 ns tOV4 Output Valid 10 Min. Typ. Max. 400/40 20 Units ns 25 ns Table 13. PHY Mode MII Timing Parameters October 2011 82 M9999-102611-3.
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Micrel, Inc. KS8995MA/FQ Timing Diagrams (Continued) Figure 21. SPI Input Timing Symbol Parameter Min. Typ. Max.
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Micrel, Inc. KS8995MA/FQ Timing Diagrams (Continued) Figure 22. SPI Output Timing Symbol Parameter Min. fC Clock Frequency tCLQX SPIQ Hold Time tCLQV Clock Low to SPIQ Valid tCH Clock High Time 90 ns tCL Clock Low Time 90 ns tQLQH SPIQ Rise Time 50 ns tQHQL SPIQ Fall Time 50 ns tSHQZ SPIQ Disable Time 100 ns 0 Typ. Max. Units 5 MHz 0 ns 60 ns Table 15. SPI Output Timing Parameters October 2011 84 M9999-102611-3.
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Micrel, Inc. KS8995MA/FQ Timing Diagrams (Continued) Figure 23. Reset Timing Symbol Parameter Min. Typ. Max. Units tSR Stable Supply Voltages to Reset High 10 ms tCS Configuration Set-Up Time 50 ns tCH Configuration Hold Time 50 ns tRC Reset to Strap-In Pin Output 50 ns Table 16. Reset Timing Parameters October 2011 85 M9999-102611-3.
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Micrel, Inc. KS8995MA/FQ Reset Circuit Diagram Micrel recommends the following discrete reset circuit as shown in Figure 24 when powering up the KS8895MA device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 25. Figure 24. Recommended Reset Circuit Figure 25.
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Micrel, Inc. KS8995MA/FQ Selection of Isolation Transformer(1) One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Value Turns Ratio Test Condition 1 CT : 1 CT Open-Circuit Inductance (min.) 350µH 100mV, 100kHz, 8mA Leakage Inductance (max.) 0.4µH 1MHz (min.
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Micrel, Inc. KS8995MA/FQ Package Information 128-Pin PQFP (PQ) October 2011 88 M9999-102611-3.
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Micrel, Inc. KS8995MA/FQ MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice.