Datasheet
2016 Microchip Technology Inc. DS00002246A-page 83
KSZ8895MQX/RQX/FQX/MLX
4.8 MIIM Registers
All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms
are used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for Port 1, “0x2” for Port 2, “0x3” for Port
3, “0x4” for Port 4, and “0x5” for Port 5. The “REGAD” supported are 0x0-0x5 (0h-5h), 0x1D (1dh) and 0x1F (1fh).
TABLE 4-12: MIIM REGISTERS
Address Name Description Mode Default
Register 0h: MII Control
15 Soft Reset
1, PHY soft reset.
0, Normal operation.
R/W
(SC)
0
14 Loopback
1 = Perform MAC loopback, loopback path as follows:
Assume the loopback is at Port 1 MAC, Port 2 is the
monitor port.
Port 1 MAC Loopback (Port 1 reg. 0, bit 14 = ‘1’)
Start: RXP2/RXM2 (Port 2). Can also start from
port 3, 4, 5
Loopback: MAC/PHY interface of Port 1’s MAC
End: TXP2/TXM2 (Port 2). Can also end at Ports
3, 4, 5 respectively
Setting address ox3,4,5 reg. 0, bit 14 = ‘1’ will per-
form MAC loopback on Ports 3, 4, 5 respectively.
0 = Normal Operation.
R/W 0
13 Force 100
1, 100 Mbps.
0, 10 Mbps.
R/W 1
12 AN Enable
1, Auto-negotiation enabled.
0, Auto-negotiation disabled.
R/W 1
11 Power Down
1, Power down.
0, Normal operation.
R/W 0
10 PHY Isolate
1, Electrical PHY isolation of PHY from Tx+/Tx-.
0, Normal operation.
R/W 0
9Restart AN
1, Restart Auto-negotiation.
0, Normal operation.
R/W 0
8
Force Full
Duplex
1, Full duplex.
0, Half duplex.
R/W 0
7 Collision Test Not supported. RO 0
6 Reserved — RO 0
5 Hp_mdix
1 = HP Auto MDI/MDI-X mode
0 = Microchip Auto MDI/MDI-X mode
R/W 1
4Force MDI
1, Force MDI.
0, Normal operation. (MDI-X transmit on TXP/TXM pair)
R/W 0
3
Disable Auto
MDI/MDI-X
1, Disable Auto MDI/MDI-X.
0, Enable Auto MDI/MDI-X.
R/W 0
2
Disable far
End fault
1, Disable far end fault detection.
0, Normal operation.
R/W 0
1
Disable
Transmit
1, Disable transmit.
0, Normal operation.
R/W 0
0 Disable LED
1, Disable LED.
0, Normal operation.
R/W 0
Register 1h: MII Status
15 T4 Capable 0, Not 100 BASET4 capable. RO 0
14
100 Full
Capable
1, 100BASE-TX full-duplex capable.
0, Not capable of 100BASE-TX full-duplex.
RO 1