Datasheet
KSZ8895MQX/RQX/FQX/MLX
DS00002246A-page 82 2016 Microchip Technology Inc.
The KSZ8895MQX/RQX/FQX/MLX provides a total of 34 MIB counter per port. These counter are used to monitor the
port detail activity for network management and maintenance. These MIB counters are read using indirect memory
access as illustrated in the following examples:
Programming Examples: (Note 4-2)
1. MIB counter read (read port 1 Rx64Octets counter)
Write to Register 110 with 0x1c (read MIB counters selected)
Write to Register 111 with 0xe (trigger the read operation)
Then
Read Register 117 (counter value 31-24)
// If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
Read Register 118 (counter value 23-16)
Read Register 119 (counter value 15-8)
Read Register 120 (counter value 7-0)
2. MIB counter read (read port 2 Rx64Octets counter)
Write to Register 110 with 0x1c (read MIB counter selected)
Write to Register 111 with 0x2e (trigger the read operation)
Then
Read Register 117 (counter value 31-24)
//If bit 31 = 1, there was a counter overflow
//If bit 30 = 0, restart (reread) from this register
Read Register 118 (counter value 23-16)
Read Register 119 (counter value 15-8)
Read Register 120 (counter value 7-0)
3. MIB counter read (read port 1 tx drop packets)
Write to Register 110 with 0x1d
Write to Register 111 with 0x00
Then
Read Register 119 (counter value 15-8)
Read Register 120 (counter value 7-0)
Note 4-2 To read out all the counters, the best performance over the SPI bus is (160+3) × 8 × 80 = 104 µs,
where there are 255 registers, three overhead, eight clocks per access, at 12.5 MHz. In the heaviest
condition, the byte counter will overflow in two minutes. It is recommended that the software read all
the counters at least every 30 seconds. The per port MIB counters are designed as “read clear.” A
per port MIB counter will be cleared after it is accessed. All port dropped packet MIB counters are
not cleared after they are accessed. The application needs to keep track of overflow and valid
conditions on these counters.