Datasheet

KSZ8895MQX/RQX/FQX/MLX

DS00002246A-page 78  2016 Microchip Technology Inc.

Read Register 116 (0x74), (Register116 [6:0] are bits 12-6 of VLAN VID=2 entry)

Read Register 117 (0x75), (Register117 [7:2] are bits 5-0 of VLAN VID=2 entry)

2. VLAN Table Write (write the VID=10 entry)

Read the VLAN set that contains VID=8, 9, 10, 11.

Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)

Write to Register 111 (0x6F) with 0x02 (trigger the read operation and VID=8, 9, 10, 11 indirect address)

Read the VLAN set first by the indirect data Registers 114, 115, 116, 117, 118, 119, and 120.

Modify the indirect data registers bits [38-26] by the Register 116 bit [6-0] and Register 117 bit [7-2] as

follows:

Write to Register 116 (0x74), (Register116 [6:0] are bits 12-6 of VLAN VID=10 entry)

Write to Register 117 (0x75), (Register117 [7:2] are bits 5-0 of VLAN VID=10 entry)

Then write the indirect control and address registers:

Write to Register 110 (0x6E) with 0x04 (write VLAN table selected)

Write to Register 111 (0x6F) with 0x02 (trigger the write operation and VID=8, 9, 10, 11 indirect address)

Table 4-9 illustrates the relationship of the indirect address/data registers and VLAN ID.

TABLE 4-9: VLAN ID AND INDIRECT REGISTERS

Indirect Address

High/Low Bit[9-0]

for VLAN Sets

Indirect Data

Each VLAN Entry

VID Numbers

VID Bit[12-2] in

VLAN Tag

VID Bit[1-0] in VLAN

Tag

0 Bits [12-0] 0 0 0

0 Bits [25-13] 1 0 1

0 Bits [38-26] 2 0 2

0 Bits [51-39] 3 0 3

1 Bits [12-0] 4 1 0

1 Bits [25-13] 5 1 1

1 Bits [38-26] 6 1 2

1 Bits [51-39] 7 1 3

2 Bits [12-0] 8 2 0

2 Bits [25-13] 9 2 1

2 Bits [38-26] 10 2 2

2 Bits [51-39] 11 2 3

:::::

1023 Bits [12-0] 4092 1023 0

1023 Bits [25-13] 4093 1023 1

1023 Bits [38-26] 4094 1023 2

1023 Bits [51-39] 4095 1023 3