Datasheet
2016 Microchip Technology Inc. DS00002246A-page 77
KSZ8895MQX/RQX/FQX/MLX
4.5 VLAN Table
The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit 7 = 1), this table is used
to retrieve VLAN information that is associated with the ingress packet. There are three fields for FID (filter ID), Valid,
and VLAN membership in the VLAN table. The three fields must be initialized before the table is used. There is no VID
field because 4096 VIDs are used as a dedicated memory address index into a 1024x52-bit memory space. Each entry
has four VLANs. Each VLAN has 13 bits. Four VLANs need 52 bits. There are a total of 1024 entries to support a total
of 4096 VLAN IDs by using dedicated memory address and data bits. Refer to Ta ble 4 -8 for details. FID has 7-bits to
support 128 active VLANs.
If 802.1q VLAN mode is enabled, KSZ8895 assigns a VID to every ingress packet when the packet is untagged or
tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with
non-null VID, the VID in the tag is used. The look-up process starts from the VLAN table look-up based on VID number
with its dedicated memory address and data bits. If the entry is not valid in the VLAN table, the packet is dropped and
no address learning occurs. If the entry is valid, the FID is retrieved. The FID+DA and FID+SA lookups in MAC tables
are performed. The FID+DA look-up determines the forwarding ports. If FID+DA fails for look-up in the MAC table, the
packet is broadcast to all the members or specified members (excluding the ingress port) based on the VLAN table. If
FID+SA fails, the FID+SA is learned. To communicate between different active VLANs, set the same FID; otherwise set
a different FID.
The VLAN table configuration is organized as 1024 VLAN sets, each VLAN set consists of four VLAN entries, to support
up to 4096 VLAN entries. Each VLAN set has 52 bits and should be read or written at the same time specified by the
indirect address.
The VLAN entries in the VLAN set is mapped to indirect data registers as follow:
• Entry0[12:0] maps to the VLAN set bits [12-0] {Register119[4:0], Register120[7:0]}
• Entry1[12:0] maps to the VLAN set bits [25-13]{Register117[1:0], Register118[7:0], Register119[7:5]}
• Entry2[12:0] maps to the VLAN set bits [38-26]{Register116[6:0], Register117[7:2]}
• Entry3[12:0] maps to the VLAN set bits [51-39]{Register114[3:0], Register115[7:0], Register116[7]}
In order to read one VLAN entry, the VLAN set is read first and the specific VLAN entry information can be extracted.
To update any VLAN entry, the VLAN set is read first then only the desired VLAN entry is updated and the whole VLAN
set is written back. Due to FID in VLAN table is 7-bit, so the VLAN table supports unique 128 flow VLAN groups. Each
VLAN set address is 10 bits long (Maximum is 1024) in the indirect address Register 110 and 111, the bits [9-8] of VLAN
set address is at bits [1-0] of Register 110, and the bit [7-0] of VLAN set address is at bits [7-0] of Register 111. Each
Write and Read can access to four consecutive VLAN entries.
Examples:
1. VLAN Table Read (read the VID=2 entry)
Write the indirect control and address registers first
Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)
Write to Register 111 (0x6F) with 0x0 (trigger the read operation for VID=0, 1, 2, 3 entries)
Then read the indirect data registers bits [38-26] for VID=2 entry:
TABLE 4-8: VLAN TABLE
Address Name Description Mode
Initial Value
Suggestion
12 Valid
1, the entry is valid.
0, entry is invalid.
R/W 0
11 - 7 Membership
Specify which ports are members of the VLAN.
If a DA look-up fails (no match in both static and
dynamic tables), the packet associated with this VLAN
will be forwarded to ports specified in this field.
E.g., 11001 means port 5, port 4 and port 1.
R/W 11111
6 - 0 FID
Filter ID. KSZ8895 supports 128 active VLANs repre-
sented by these seven bit fields. FID is the mapped ID.
If 802.1q VLAN is enabled, the look-up in MAC table will
be based on FID+DA and FID+SA.
R/W 0