Datasheet

KSZ8895MQX/RQX/FQX/MLX
DS00002246A-page 74  2016 Microchip Technology Inc.
Note 4-1 In the priority 0-3 ingress rate limit mode, there is a need to set all related ingress/egress port to two
queues or four queues mode.
Note 4-2 In the port queue 0-3 egress rate limit mode, the highest priority get exact rate limit based on the
rate select table, other priorities packets rate are based up on the ratio of the Register Port Control
10/11/12/13 when use more than one egress queue per port.
4
Invert phase of
SMRXC clock
output on SW5-
RMII for RQX
part
1 = Invert the phase of SMRXC clock output in
RMII mode that will add opposite RMII output
delay 10ns from clock rising edge to data out.
0 = normal phase if SMRXC clock output
Note: MQX and FQX are reserved with read
only for this bit.
R/W 0
3 - 0 Reserved N/A Do not change RO 0
TABLE 4-5: 10/100BT RATE SELECTION FOR THE RATE LIMIT
Data Rate Limit for
Ingress or Egress
100BT
Priority/Queue 0-3 Ingress/egress limit
Control Register bit [6:0] = decimal;
1Mbps ≤ rate ≤ 99 Mbps
rate (decimal integer 1-99);
0 or 100 (decimal), ‘0’ is default value
100BT
Priority/Queue 0-3 Ingress/egress limit
Control Register bit [6:0] = decimal;
1Mbps ≤ rate ≤ 9Mbps
rate (decimal integer 1-9);
0 or 100 (decimal), ‘0’ is default value
Less than 1 Mbps, see
below
Decimal
64 kbps 7’d101
128 kbps 7’d102
192 kbps 7’d103
256 kbps 7’d104
320 kbps 7’d105
384 kbps 7’d106
448 kbps 7’d107
512 kbps 7’d108
576 kbps 7’d109
640 kbps 7’d110
704 kbps 7’d111
768 kbps 7’d112
832 kbps 7’d113
896 kbps 7’d114
960 kbps 7’d115
TABLE 4-4: ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode Default