Datasheet

 2016 Microchip Technology Inc. DS00002246A-page 73
KSZ8895MQX/RQX/FQX/MLX
6 - 0
Port Queue 1
Egress Limit
Egress data rate limit for priority 1 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See
the table follow the end of Egress limit control
registers.
In four queues mode, it is low/high priority.
In two queues mode, it is high priority.
R/W 0000000
Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3
Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3
Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3
Register 237 (0xED): Port 4 Queue 2 Egress Limit Control 3
Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3
7 Reserved — RO 0
6 - 0
Port Queue 2
Egress Limit
Egress data rate limit for priority 2 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See
the table follow the end of Egress limit control
registers.
In four queues mode, it is high/low priority.
R/W 0000000
Register 190 (0xBE): Port 1 Queue 3 Egress Limit Control 4
Register 206 (0xCE): Port 2 Queue 3 Egress Limit Control 4
Register 222 (0xDE): Port 3 Queue 3 Egress Limit Control 4
Register 238 (0xEE): Port 4 Queue 3 Egress Limit Control 4
Register 254 (0xFE): Port 5 Queue 3 Egress Limit Control 4
7 Reserved — RO 0
6 - 0
Port Queue 3
Egress Limit
(Note 4-1,
Note 4-2)
Egress data rate limit for priority 3 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See
the table follow the end of Egress limit control
registers.
In four queues mode, it is highest priority.
R/W 0000000
Register 191 (0xBF): Testing Register 1
7 - 0 Reserved N/A Do not change RO 0x80
Register 207 (0xCF): Reserved Control Register
7 - 0 Reserved N/A Do not change RO 0x15
Register 223 (0xDF): Testing Register 2
7 - 0 Reserved N/A Do not change RO 0x0C
Register 239 (0xEF): Port 3 Copper or Fiber Control
7
Fiber select for
Port 3
0 = Port 3 is copper port (default)
1 = Port 3 is fiber port.
R/W 0
Reserved N/A Do not change RO 0110010
Register 255 (0xFF): Testing Register 3
7 Reserved N/A Do not change RO 0
6
Invert phase of
SMTXC clock
input on SW5-
RMII for RQX
part
1 = Invert the phase of SMTXC clock input in
RMII mode, use falling edge to clock output data
internally that will add KSZ8995RQX output
delay 10ns if SMRXC is not inverted.
0 = normal phase if SMTXC clock input
Note: MQX and FQX are reserved with read
only for this bit.
R/W 0
5 Reserved N/A Do not change RO 0
TABLE 4-4: ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode Default