Datasheet
2016 Microchip Technology Inc. DS00002246A-page 69
KSZ8895MQX/RQX/FQX/MLX
3
Insert Source
Port PVID for
Untagged
Packet Destina-
tion to Highest
Egress Port
Register 176: insert source Port 1 PVID for
untagged frame at egress Port 5
Register 192: insert source Port 2 PVID for
untagged frame at egress Port 5
Register 208: insert source Port 3 PVID for
untagged frame at egress Port 5
Register 224: insert source Port 4 PVID for
untagged frame at egress Port 5
Register 240: insert source Port 5 PVID for
untagged frame at egress Port 4
Note: Enabled by the Register 135 bit 2
R/W 0
2
Insert Source
Port PVID for
Untagged
Packet Destina-
tion to Second
Highest Egress
Port
Register 176: insert source Port 1 PVID for
untagged frame at egress Port 4
Register 192: insert source Port 2 PVID for
untagged frame at egress Port 4
Register 208: insert source Port 3 PVID for
untagged frame at egress Port 4
Register 224: insert source Port 4 PVID for
untagged frame at egress Port 3
Register 240: insert source Port 5 PVID for
untagged frame at egress Port 3
Note: Enabled by the Register 135 bit 2
R/W 0
1
Insert Source
Port PVID for
Untagged
Packet Destina-
tion to Second
Lowest Egress
Port
Register 176: insert source Port 1 PVID for
untagged frame at egress Port 3
Register 192: insert source Port 2 PVID for
untagged frame at egress Port 3
Register 208: insert source Port 3 PVID for
untagged frame at egress Port 2
Register 224: insert source Port 4 PVID for
untagged frame at egress Port 2
Register 240: insert source Port 5 PVID for
untagged frame at egress Port 2
Note: Enabled by the Register 135 bit 2
R/W 0
0
Insert Source
Port PVID for
Untagged
Packet Destina-
tion to Lowest
Egress Port
Register 176: insert source Port 1 PVID for
untagged frame at egress Port 2
Register 192: insert source Port 2 PVID for
untagged frame at egress Port 1
Register 208: insert source Port 3 PVID for
untagged frame at egress Port 1
Register 224: insert source Port 4 PVID for
untagged frame at egress Port 1
Register 240: insert source Port 5 PVID for
untagged frame at egress Port 1
Note: Enabled by the Register 135 bit 2
R/W 0
Register 177 (0xB1): Port 1 Control 9
Register 193 (0xC1): Port 2 Control 9
Register 209 (0xD1): Port 3 Control 9
Register 225 (0xE1): Port 4 Control 9
Register 241 (0xF1): Port 5 Control 9
7 - 2 Reserved — RO 000000
TABLE 4-4: ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode Default