Datasheet
2016 Microchip Technology Inc. DS00002246A-page 61
KSZ8895MQX/RQX/FQX/MLX
Note 4-1 Bits 2-0 are used for spanning tree support. See “Spanning Tree Support” section for more
information.
Note 4-2 Registers 19 and 20 (and those corresponding to other ports) serve two purposes: (1) Associated
with the ingress untagged packets, and used for egress tagging; (2) Default VID for the ingress
untagged or null-VID-tagged packets, and used for address look up.
Note 4-3 Port Control 12, 13, 14 and Port Status 1, 2 contents can be accessed by MIIM (MDC/MDIO) interface
via the standard MIIM register definition.
4.3 Advanced Control Registers
Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in
MAC pause control frames, or is used for self MAC address filtering, also see Register 134. Use Registers 110 and 111
to read or write data to the static MAC address table, VLAN table, dynamic address table, or the MIB counters. Write to
Register 111 will actually trigger a command. Read or write access will be decided by bit 4 of Register 110. Registers
128 and 129 can be used to map from 802.1p priority field 0-7 to switch’s four priority queues 0-3, 0x3 is highest priority
queues as priority 3, 0x0 is lowest priority queues as priority 0.
Register 31 (0x1F): Port 1 Control 7 and Status 2
Register 47 (0x2F): Port 2 Control 7 and Status 2
Register 63 (0x3F): Port 3 Control 7 and Status 2
Register 79 (0x4F): Port 4 Control 7 and Status 2
Register 95 (0x5F): Port 5 Control 7 and Status 2
7
PHY
Loopback
1 = Perform PHY loopback, loop back path as fol-
lows:
E.g. set port 1 PHY Loopback (reg. 31, bit 7 = ‘1’)
Use the port 2 as monitor port. The packets will
transfer.
Start: Port 2 receiving (also can start from
port 3, 4, 5).
Loopback: PMD/PMA of Port 1’s PHY
End: Port 2 transmitting (also can end at Port
3, 4, 5 respectively).
Setting reg. 47, 63, 79, 95, bit 7 = ‘1’ will per-
form PHY loopback on port 2, 3, 4, 5 respectively.
0 = Normal Operation.
R/W 0
6 Reserved N/A Do not change RO 0
5 PHY Isolate
1, Electrical isolation of PHY from MII/RMII and
TX+/TX-.
0, Normal operation.
R/W 0
4 Soft Reset
1, PHY soft reset. This bit is self-clearing.
0, normal operation.
R/W
(SC)
0
3 Force Link
1, force link in the PHY.
0, normal operation
R/W 0
2 - 0
Port Opera-
tion Mode
Indication
Indicate the current state of port operation mode:
[000] = Reserved
[001] = still in auto-negotiation
[010] = 10BASE-T half-duplex
[011] = 100BASE-TX half-duplex
[100] = Reserved
[101] = 10BASE-T full-duplex
[110] = 100BASE-TX full-duplex
[111] = Reserved
RO 001
TABLE 4-3: PORT REGISTERS (CONTINUED)
Address Name Description Mode Default