Datasheet

KSZ8895MQX/RQX/FQX/MLX
DS00002246A-page 56  2016 Microchip Technology Inc.
4
Force Flow
Control
1, will always enable Rx and Tx flow control on the
port, regardless of AN result.
0, the flow control is enabled based on AN result
(Default)
R/W
0
Strap-in option
LED1_1/PCOL: For
port 3/port 4 LED1_1
default Pull-up (1):
Not force flow control;
PCOL default Pull-
down (0): Not force
flow control. LED1_1
Pull-down (0): Force
flow control; PCOL
Pull-up (1): Force flow
control.
Note: LED1_1 has
internal pull-up;
PCOL have internal
pull-down.
3
Back Pres-
sure Enable
1, enable port half-duplex back pressure.
0, disable port half-duplex back pressure.
R/W
Pin PMRXD2 strap
option.
Pull-down (0): dis-
able back pressure.
Pull-up (1): enable
back pressure.
Note: PMRXD2 has
internal pull-down.
2
Transmit
Enable
1, enable packet transmission on the port.
0, disable packet transmission on the port.
R/W 1
1
Receive
Enable
1, enable packet reception on the port.
0, disable packet reception on the port.
R/W 1
0
Learning Dis-
able
1, disable switch address learning capability.
0, enable switch address learning.
R/W 0
Register 19 (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Register 67 (0x43): Port 4 Control 3
Register 83 (0x53): Port 5 Control 3
7 - 0
Default Tag
[15:8]
Port’s default tag, containing:
7-5: user priority bits
4: CFI bit
3-0: VID[11:8]
R/W 0
Register 20 (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Register 52 (0x34): Port 3 Control 4
Register 68 (0x44): Port 4 Control 4
Register 84 (0x54): Port 5 Control 4
7 - 0
Default Tag
[7:0]
Default port 1’s tag, containing:
7-0: VID[7:0]
R/W 1
Register 87 (0x57): RMII Management Control Register
7 - 4 Reserved — RO 0000
TABLE 4-3: PORT REGISTERS (CONTINUED)
Address Name Description Mode Default