Datasheet
2016 Microchip Technology Inc. DS00002246A-page 51
KSZ8895MQX/RQX/FQX/MLX
6
Switch SW5-
MII/RMII
Half-Duplex
Mode
1, enable MII/RMII interface half-duplex mode.
0, disable MII/RMII interface full-duplex mode.
R/W
0
Pin SMRXD2 strap
option.
PD(0): (default) Full-
duplex mode.
PU(1): Half-duplex
mode. Note:
SMRXD2 has
internal pull-down.
5
Switch SW5-
MII/RMII
Flow Control
Enable
1, enable full-duplex flow control on switch MII/
RMII interface.
0, disable full-duplex flow control on switch MII/
RMII interface.
R/W
0
Pin SMRXD3 strap
option.
PD(0): (default)
Disable flow control.
PU(1): enable flow
control.
Note: SMRXD3
has internal
pull-down.
4
Switch SW5-
MII/RMII
Speed
1, the switch SW5-MII/RMII is in 10 Mbps mode.
0, the switch SW5-MII/RMII is in 100 Mbps mode
R/W
0
Pin SMRXD1 strap
option.
PD(0): (default)
Enable 100 Mbps.
PU(1): Enable
10 Mbps.
Note: SMRXD1 has
internal pull-down.
3
Null VID
Replacement
1, will replace null VID with port VID (12 bits).
0, no replacement for null VID.
R/W 0
2 - 0
Broadcast
Storm
Protection
Rate Bit
[10:8]
This along with the next register determines how
many “64 byte blocks” of packet data allowed on an
input port in a preset period. The period is 50 ms
for 100BT or 500 ms for 10BT. The default is 1%.
R/W 000
Register 7 (0x07): Global Control 5
7 - 0
Broadcast
Storm
Protection
Rate Bit [7:0]
This along with the previous register determines
how many “64 byte blocks” of packet data are
allowed on an input port in a preset period. The
period is 50 ms for
100BT or 500ms for 10BT. The default is 1%.
R/W
0x4A
(Note 4-1)
Register 8 (0x08): Global Control 6
7 - 0
Factory
Testing
N/A Do not change. RO 0x00
Register 9 (0x09): Global Control 7
7 - 0
Factory
Testing
N/A Do not change RO 0x4C
Register 10 (0x0A): Global Control 8
7 - 0
Factory
Testing
N/A Do not change RO 0x00
Register 11 (0x0B): Global Control 9
7 Reserved N/A Do not change RO 0
TABLE 4-2: GLOBAL REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode Default