Datasheet

 2016 Microchip Technology Inc. DS00002246A-page 45
KSZ8895MQX/RQX/FQX/MLX
per port.
The MIIM Interface can operate up to a maximum clock speed of 10 MHz MDC clock.
Table 3-12 depicts the MII Management Interface frame format.
The MIIM interface does not have access to all the configuration registers in the KSZ8895MQX/RQX/FQX/MLX. It can
only access the standard MIIM registers. See “MIIM Registers”. The SPI interface and MDC/MDIO SMI mode, on the
other hand, can be used to access all registers with the entire KSZ8895MQX/RQX/FQX/MLX feature set.
3.7 Serial Management Interface (SMI)
The SMI is the KSZ8895MQX/RQX/FQX/MLX non-standard MIIM interface that provides access to all KSZ8895MQX/
RQX/FQX/MLX configuration registers. This interface allows an external device with MDC/MDIO interface to completely
monitor and control the states of the KSZ8895MQX/RQX/FQX/MLX.
The SMI interface consists of the following:
• A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8895MQX/RQX/FQX/MLX device.
• Access all KSZ8895MQX/RQX/FQX/MLX configuration registers. Register access includes the Global, Port and
Advanced Control Registers 0-255 (0x00 – 0xFF), and indirect access to the standard MIIM Registers [0:5] and
custom MIIM Registers [29, 31].
The SMI Interface can operate up to a maximum clock speed of 10 MHz MDC clock.
Table 3-13 depicts the SMI frame format.
SMI register read access is selected when OP Code is set to “10” and bits [2:1] of the PHY address is set to ‘11’. The
8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit [4:0]}. TA
is turn-around bits. TA bits [1:0] are ’Z0’ means the processor MDIO pin is changed to input Hi-Z from output mode and
the followed ‘0’ is the read response from device, as the switch configuration registers are 8-bit wide, only the lower 8
bits of data bits [15:0] are used
SMI register Write access is selected when OP Code is set to “01” and bits [2:1] of the PHY address is set to ‘11’. The
8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit [4:0]}. TA
bits [1:0] are set to ‘10’, as the switch configuration registers are 8-bit wide, only the lower 8 bits of data bits [15:0] are
used.
To access the KSZ8895MQX/RQX/FQX/MLX Registers 0-255 (0x00 - 0xFF), the following applies:
• PHYAD [4, 3, 0] and REGAD [4:0] are concatenated to form the 8-bit address; that is, {PHYAD [4, 3, 0], REGAD
[4:0]} = bits [7:0] of the 8-bit address.
• Registers are 8 data bits wide. For read operation, data bits [15:8] are read back as zeroes. For write operation,
data bits [15:8] are not defined, and hence can be set to either zeroes or ones.
SMI register access is the same as the MIIM register access, except for the register access requirements presented in
this section.
TABLE 3-12: MII MANAGEMENT FRAME FORMAT
— Preamble
Start of
Frame
Read/
Write OP
Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
TA Data Bits[15:0] Idle
Read 32 1’s 01 10 AAAAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 AAAAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
TABLE 3-13: SERIAL MANAGEMENT INTERFACE (SMI) FRAME FORMAT
— Preamble
Start of
Frame
Read/
Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA Data Bits[15:0] Idle
Read 32 1’s 01 10 RR11R RRRRR Z0 0000_0000_DDDD_DDDD Z
Write 32 1’s 01 01 RR11R RRRRR 10 xxxx_xxxx_DDDD_DDDD Z