Datasheet

KSZ8895MQX/RQX/FQX/MLX
DS00002246A-page 44  2016 Microchip Technology Inc.
3.6 MII Management (MIIM) Interface
The KSZ8895MQX/RQX/FQX/MLX supports the standard IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the
states of the KSZ8895MQX/RQX/FQX/MLX. An external device with MDC/MDIO capability is used to read the PHY sta-
tus or configure the PHY settings. Further details on the MIIM interface are found in Clause 22.2.4.5 of the IEEE 802.3u
Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the data line (Pin108 MDIO) and the clock line (Pin107 MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8895MQX/RQX/FQX/MLX device.
• Access to a set of eight 16-bit registers, consisting of 8 standard MIIM Registers [0:5h], 1d and 1f MIIM registers
FIGURE 3-13: SPI MULTIPLE WRITE
FIGURE 3-14: SPI MULTIPLE READ