Datasheet

KSZ8895MQX/RQX/FQX/MLX
DS00002246A-page 42  2016 Microchip Technology Inc.
To configure the KSZ8895MQX/RQX/FQX/MLX with a pre-configured EEPROM use the following steps:
1. At the board level, connect Pin 110 on the KSZ8895MQX/RQX/FQX/MLX to the SCL pin on the EEPROM. Con-
nect Pin 111 on the KSZ8895MQX/RQX/FQX/MLX to the SDA pin on the EEPROM.
2. A [2-0] address pins of EEPROM should be tied to ground for A [2-0] = ‘000’ to be identified by the KSZ8895MQX/
RQX/FQX/MLX.
3. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00.” This puts the KSZ8895MQX/RQX/FQX/
MLX serial bus configuration into I
2
C master mode.
4. Be sure the board-level reset signal is connected to the KSZ8895MQX/RQX/FQX/MLX reset signal on Pin115
(RST_N).
5. Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note
that the first byte in the EEPROM must be “95” for the loading to occur properly. If this value is not correct, all
other data will be ignored.
6. Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on the
KSZ8895MQX/RQX/FQX/MLX. After the reset is de-asserted, the KSZ8895MQX/RQX/FQX/MLX will begin read-
ing configuration data from the EEPROM. The configuration access time (t
prgm
) is less than 30 ms.
Please note that for proper operation, make sure that Pin 47 (PWRDN_N) is not asserted during the reset operation.
3.5.10.2 SPI Slave Serial Bus Configuration
The KSZ8895MQX/RQX/FQX/MLX can also act as a SPI slave device. Through the SPI, the entire feature set can be
enabled, including “VLAN,” “IGMP snooping,” “MIB counters,” etc. The external master device can access any register
from Register 0 to Register 255 randomly. The system should configure all the desired settings before enabling the
switch in the KSZ8895MQX/RQX/FQX/MLX. To enable the switch, write a ‘1’ to Register 1 bit 0.
Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To speed
configuration time, the KSZ8895MQX/RQX/FQX/MLX also supports multiple reads or writes. After a byte is written to or
read from the KSZ8895MQX/RQX/FQX/MLX, the internal address counter automatically increments if the SPI Slave
Select Signal (SPIS_N) continues to be driven low. If SPIS_N is kept low after the first byte is read, the next byte at the
next address will be shifted out on SPIQ. If SPIS_N is kept low after the first byte is written, bits on the Master Out Slave
Input (SPID) line will be written to the next address. Asserting SPIS_N high terminates a read or write operation. This
means that the SPIS_N signal must be asserted high and then low again before issuing another command and address.
The address counter wraps back to zero once it reaches the highest address. Therefore the entire register set can be
written to or read from by issuing a single command and address.
The default SPI clock speed is 12.5 MHz. The KSZ8895MQX/RQX/FQX/MLX is able to support a SPI bus up to 25 MHz
(set Register 12 bit [5:4] = 0x10). A high performance SPI master is recommended to prevent internal counter overflow.
To use the KSZ8895MQX/RQX/FQX/MLX SPI:
1. At the board level, connect KSZ8895MQX/RQX/FQX/MLX pins as follows:
FIGURE 3-10: EEPROM CONFIGURATION TIMING DIAGRAM
TABLE 3-11: SPI CONNECTIONS
Pin Number Signal Name Microprocessor Signal Description
112 SPIS_N SPI Slave Select