Datasheet
2016 Microchip Technology Inc. DS00002246A-page 33
KSZ8895MQX/RQX/FQX/MLX
3.4.17 PORT 5 MAC 5 SW5-MII INTERFACE FOR THE KSZ8895MQX/FQX/MLX
Table 3-5 shows two connection manners:
• The first is an external MAC connects to SW5-MII PHY mode.
• The second is an external PHY connects to SW5-MII MAC mode.
Please see the pin [91, 86, 87] descriptions for configuration details for the MAC mode and PHY mode. SW5-MII works
with 25 MHz clock for 100BASE-TX, SW5-MII works with 2.5 MHz clock for 10BASE-T.
The switch MII interface operates in either MAC mode or PHY mode for KSZ8895MQX/FQX/MLX. These interfaces are
nibble-wide data interfaces, so they run at one-quarter the network bit rate (not encoded). Additional signals on the
transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has
indicators that convey when the data is valid and without physical layer errors. For half-duplex operation, there is a sig-
nal that indicates a collision has occurred during transmission.
Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is
not provided on the SW-MII interface for MAC mode operation. Normally MRXER would indicate a receive error coming
from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not
appropriate for this configuration. For PHY mode operation with an external MAC, if the device interfacing with the
KSZ8895MQX/FQX/MLX has an MRXER pin, it should be tied low. For MAC mode operation with an external PHY, if
the device interfacing with the KSZ8895MQX/FQX/MLX has an MTXER pin, it should be tied low.
TABLE 3-5: SWITCH MAC5 MII SIGNALS
KSZ8895MQX/FQX/MLX PHY Mode
Connection
Description
KSZ8895MQX/FQX/MLX MAC Mode
Connection
External MAC
SW5-MII
Signals
Type External PHY
SW5-MII
Signals
Type
MTXEN SMTXEN Input
Transmit
enable
MTXEN SMRXDV Output
MTXER SMTXER Input Transmit error MTXER Not used Not used
MTXD3 SMTXD[3] Input
Transmit data
bit 3
MTXD3 SMRXD[3] Output
MTXD2 SMTXD[2] Input
Transmit data
bit 2
MTXD2 SMRXD[2] Output
MTXD1 SMTXD[1] Input
Transmit data
bit 1
MTXD1 SMRXD[1] Output
MTXD0 SMTXD[0] Input
Transmit data
bit 0
MTXD0 SMRXD[0] Output
MTXC SMTXC Output Transmit clock MTXC SMRXC Input
MCOL SCOL Output
Collision
detection
MCOL SCOL Input
MCRS SCRS Output Carrier sense MCRS SCRS Input
MRXDV SMRXDV Output
Receive data
valid
MRXDV SMTXEN Input
MRXER Not used Output Receive error MRXER SMTXER Input
MRXD3 SMRXD[3] Output
Receive data
bit 3
MRXD3 SMTXD[3] Input
MRXD2 SMRXD[2] Output
Receive data
bit 2
MRXD2 SMTXD[2] Input
MRXD1 SMRXD[1] Output
Receive data
bit 1
MRXD1 SMTXD[1] Input
MRXD0 SMRXD[0] Output
Receive data
bit 0
MRXD0 SMTXD[0] Input
MRXC SMRXC Output Receive clock MRXC SMTXC Input