Datasheet
KSZ8895MQX/RQX/FQX/MLX
DS00002246A-page 32 2016 Microchip Technology Inc.
• Aggressive back-off (Register 3, bit 0)
• No excessive collision drop (Register 4, bit 3)
• Back pressure (Register 4, bit 5)
These bits are not set as the default because they are not the IEEE standard.
3.4.14 BROADCAST STORM PROTECTION
The KSZ8895MQX/RQX/FQX/MLX has an intelligent option to protect the switch system from receiving too many broad-
cast packets. Broadcast packets are normally forwarded to all ports except the source port and thus use too many switch
resources (bandwidth and available space in transmit queues). The KSZ8895MQX/RQX/FQX/MLX has the option to
include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally and can
be enabled or disabled on a per port basis. The rate is based on a 50 ms (0.05s) interval for 100BT and a 500 ms (0.5s)
interval for 10BT. At the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to
count the number of bytes during the interval. The rate definition is described in Registers 6 and 7. The default setting
for Registers 6 and 7 is 0x4A (74 decimal). This is equal to a rate of 1%, calculated as follows:
148,800 frames/sec × 50 ms (0.05s)/interval × 1% = 74 frames/interval (approx.) = 0x4A.
3.4.15 MII INTERFACE OPERATION
The media-independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface
between physical layer and MAC layer devices. The KSZ8895MQX/RQX/FQX/MLX provides two such interfaces. The
P5-MII interface is used to connect to the fifth PHY, where as the SW-MII interface is used to connect to the fifth MAC.
Each of these MII interfaces contains two distinct groups of signals, one for transmission and the other for receiving.
3.4.16 PORT 5 PHY 5 P5-MII/RMII INTERFACE
The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface
between the physical layer and MAC layer devices. The Reduced Media Independent Interface (RMII) specifies a low
pin count MII. The KSZ8895MQX/RQX/FQX/MLX provides two such interfaces for MAC5 and PHY5. The Port 5 PHY5
P5-MII/RMII interface is used to connect to the fifth PHY, where as the SW-MII/RMII interface is used to connect to the
fifth MAC. The KSZ8895MQX/FQX/MLX support P5-MII, the KSZ8895RQX supports P5-RMII. Each of these MII/RMII
interfaces contains two distinct groups of signals, one for transmission and the other for receiving. Ta b le 3 - 4 describes
the signals used in the PHY [5] P5-MII/RMII interface. The P5-MII interface operates in PHY mode only.
TABLE 3-4: PORT 5 PHY P5-MII/RMII SIGNALS
MII Signal Description
KSZ8895MQX/FQX/
MLX P5-MII
KSZ8895MQX/
FQX/MLX MII
Signal Type
KSZ8895RQX
P5-RMII
KSZ8895RQX
RMII Signal
Type
MTXEN Transmit enable PMTXEN I PMTXEN I
MTXER Transmit error PMTXER I — —
MTXD3 Transmit data bit 3 PMTXD[3] I — —
MTXD2 Transmit data bit 2 PMTXD[2] I — —
MTXD1 Transmit data bit 1 PMTXD[1] I PMTXD[1] I
MTXD0 Transmit data bit 0 PMTXD[0] I PMTXD[0] I
MTXC Transmit clock PMTXC O
PMREFCLK/
PMTXC
I
MCOL Collision detection PCOL O — —
MCRS Carrier sense PCRS O — —
MRXDV Receive data valid PMRXDV O PMRXDV O
MRXER Receive error PMRXER O PMRXER O
MRXD3 Receive data bit 3 PMRXD[3] O — —
MRXD2 Receive data bit 2 PMRXD[2] O — —
MRXD1 Receive data bit 1 PMRXD[1] O PMRXD[1] O
MRXD0 Receive data bit 0 PMRXD[0] O PMRXD[0] O
MRXC Receive clock PMRXC O PMRXC O