Datasheet

KSZ8895MQX/RQX/FQX/MLX
DS00002246A-page 100  2016 Microchip Technology Inc.
8.0 RESET CIRCUIT
A discreet reset circuit, as shown in Figure 8-1, is recommended for the power-up reset circuit.
FIGURE 8-1: RECOMMENDED RESET CIRCUIT
Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example,
the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2
is required if using different V
DDIO
voltage between switch and CPU/FPGA. Diode D2 should be selected to provide
maximum 0.3V V
F
(Forward Voltage), for example, VISHAY BAT54, MSS1P2L. Alternatively, a level shifter device can
also be used. D2 is not required if switch and CPU/FPGA use same V
DDIO
voltage.
FIGURE 8-2: RECOMMENDED RESET CIRCUIT FOR CPU/FPGA RESET OUTPUT
KSZ8895
VDDIO
D1
D1: 1N4148
5Nȍ
C 10μF
RST#
KSZ8895 CPU/FPGA
VDDIO
C 10μF
5Nȍ
RST_OUT_n
D1
D2
D1: 1N4148
RST#