Datasheet

KSZ8895MQX/RQX/FQX/MLX
DS00002246A-page 10  2016 Microchip Technology Inc.
59 VDDIO P — 3.3V, 2.5V, or 1.8V digital V
DD
for digital I/O circuitry.
60 PMRXC I/O 5
MQX/FQX/MLX: Output PHY [5] MII receive clock.
RQX: Output PHY [5] RMII reference clock, this clock is used when
opposite doesn’t provide RMII 50 MHz clock or the system doesn’t
provide an external 50 MHz clock for the P5-RMII interface.
61
PMRXDV/
PMCRSDV
IPD/O 5
MQX/FQX/MLX: PMRXDV is for PHY [5] MII receive data valid.
RQX: PMCRSDV is for PHY [5] RMII Carrier Sense/Receive Data
Valid Output.
62 PMRXD3 IPD/O 5
MQX/FQX/MLX: PHY [5] MII receive bit 3.
RQX: no connection for RMII.
Strap option:
PD (default) = enable flow control.
PU = disable flow control.
63 PMRXD2 IPD/O 5
MQX/FQX/MLX: PHY [5] MII receive bit 2.
RQX: no connection for RMII.
Strap option:
PD (default) = disable back pressure.
PU = enable back pressure.
64 PMRXD1 IPD/O 5
MQX/FQX/MLX: PHY [5] MII receive bit 1.
RQX: PHY [5] RMII receive bit 1.
Strap option:
PD (default) = drop excessive collision packets.
PU = does not drop excessive collision packets.
65 PMRXD0 IPD/O 5
MQX/FQX/MLX: PHY [5] MII receive bit 0.
RQX: PHY [5] RMII receive bit 0.
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex
mode.
PU = enable for performance enhancement.
66 PMRXER IPD/O 5
MQX/FQX/MLX:PHY [5] MII receive error
RQX: PHY [5] RMII receive error
Strap option:
PD (default) = packet size 1518/1522 bytes.
PU = 1536 bytes.
67 PCRS IPD/O 5
MQX/FQX/MLX: PHY [5] MII carrier sense.
RQX: no connection for RMII.
Strap option for port 4 only.
PD (default) = force half-duplex if auto-negotiation is disabled or
fails.
PU = force full-duplex if auto negotiation is disabled or fails. Refer to
Register 76.
68 PCOL IPD/O 5
MQX/FQX/MLX: PHY [5] MII collision detect.
RQX: no connection.
Strap option for port 4 only.
PD (default) = no force flow control, normal operation.
PU = force flow control. Refer to Register 66.
TABLE 2-1: SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED)
Pin
Number
Pin
Name
Type,
Note
2-1
Port Pin Function, Note 2-2