Datasheet

 2017 Microchip Technology Inc. DS00002348A-page 9

KSZ8873MLL/FLL/RLL

51 P3SPD Ipd/O

PU = force port 3 to 10BT

PD = force port 3 to 100BT (default)

52 NC NC Unused pin. No external connection.

53 NC NC Unused pin. No external connection.

54 VDDIO P

3.3V, 2.5V or 1.8V digital V

input power supply for IO with well decoupling

capacitors.

55 GND GND Digital ground

56 VDDCO P

1.8V core power voltage output (internal 1.8V LDO regulator output), this

1.8V output pin provides power to both VDDA_1.8 and VDDC input pins.

Note: Internally 1.8V LDO regulator input comes from VDDIO. Do not connect

an external power supply to VDDCO pin. The ferrite bead is requested

between analog and digital 1.8V core power.

57 NC NC Unused pin. No external connection.

58 P1LED1 Ipu/O

Port 1 LED Indicators:

Default: Speed (refer to register 195 bit[5:4])

Strap option: Port 3 flow control selection (P3FFC)

PU = always enable (force) port 3 flow control feature (default)

PD = disable

59 P1LED0 Ipd/O

Port 1 LED Indicators:

Default: Link/Act. (refer to Register 195 bit[5:4])

Strap option: Port 3 duplex mode selection (P3DPX)

PU = port 3 to half-duplex mode

PD = port 3 to full-duplex mode (default)

Note: P1LED0 has weaker internal pull-down, recommend an external pull-

down by a 0.5 k resistor.

TABLE 2-1: SIGNALS (CONTINUED)

Number

Name

Type

Note

2-1

Description