Datasheet

 2017 Microchip Technology Inc. DS00002348A-page 87
KSZ8873MLL/FLL/RLL
7.10 Reset Timing
The KSZ8873MLL/FLL/RLL reset timing requirement is summarized in Figure 7-17 and Tab l e 7 - 1 0 .
After the de-assertion of reset, wait a minimum of 100 µs before starting programming on the managed interface (I
2
C
slave, SPI slave, SMI, MIIM).
FIGURE 7-17: RESET TIMING
TABLE 7-10: RESET TIMING PARAMETERS
Parameter Description Min. Typ. Max. Units
t
SR
Stable supply voltages to reset high 10 — — ms
t
CS
Configuration setup time 50 — — ns
t
CH
Configuration hold time 50 — — ns
t
RC
Reset to strap-in pin output 50 — — ns
t
VR
3.3V rise time 100 — — µs
SUPPLY
VOLTAGES
RST#
STRAP-IN
VALUE
STRAP-IN /
OUTPUT PIN
t
VR
t
SR
t
CS
t
CH
t
RC