Datasheet

KSZ8873MLL/FLL/RLL
DS00002348A-page 72  2017 Microchip Technology Inc.
“All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters
are shown in Table 4-16.
0xC RxMulticast
Rx good multicast packets (not including MAC control frames, error
multicast packets or valid broadcast packets)
0xD RxUnicast Rx good unicast packets
0xE Rx64Octets Total Rx packets (bad packets included) that were 64 octets in length
0xF Rx65to127Octets
Total Rx packets (bad packets included) that are between 65 and 127
octets in length
0x10 Rx128to255Octets
Total Rx packets (bad packets included) that are between 128 and 255
octets in length
0x11 Rx256to511Octets
Total Rx packets (bad packets included) that are between 256 and 511
octets in length
0x12 Rx512to1023Octets
Total Rx packets (bad packets included) that are between 512 and
1023 octets in length
0x13 Rx1024to1522Octets
Total Rx packets (bad packets included) that are between 1024 and
1522 octets in length (upper limit depends on max packet size setting)
0x14 TxLoPriorityByte Tx lo-priority good octet count, including PAUSE packets
0x15 TxHiPriorityByte Tx hi-priority good octet count, including PAUSE packets
0x16 TxLateCollision
The number of times a collision is detected later than 512 bit-times into
the Tx of a packet
0x17 TxPausePkts Number of PAUSE frames transmitted by a port
0x18 TxBroadcastPkts
Tx good broadcast packets (not including error broadcast or valid multi-
cast packets)
0x19 TxMulticastPkts
Tx good multicast packets (not including error multicast packets or valid
broadcast packets)
0x1A TxUnicastPkts Tx good unicast packets
0x1B TxDeferred
Tx packets by a port for which the 1st Tx attempt is delayed due to the
busy medium
0x1C TxTotalCollision Tx total collision, half duplex only
0x1D TxExcessiveCollision A count of frames for which Tx fails due to excessive collisions
0x1E TxSingleCollision
Successfully Tx frames on a port for which Tx is inhibited by exactly
one collision
0x1F TxMultipleCollision
Successfully Tx frames on a port for which Tx is inhibited by more than
one collision
TABLE 4-15: FORMAT OF “ALL PORT DROPPED PACKET” MIB COUNTERS
Bit Name R/W Description Default
30-16 Reserved N/A Reserved N/A
15-0 Counter Value RO Counter Value 0
TABLE 4-16: “ALL PORT DROPPED PACKET” MIB COUNTERS INDIRECT MEMORY OFFSETS
Offset Counter Name Description
0x100 Port 1 TX Drop Packets TX packets dropped due to lack of resources
0x101 Port 2 TX Drop Packets TX packets dropped due to lack of resources
0x102 Port 3 TX Drop Packets TX packets dropped due to lack of resources
0x103 Port 1 RX Drop Packets RX packets dropped due to lack of resources
0x104 Port 2 RX Drop Packets RX packets dropped due to lack of resources
TABLE 4-14: PORT 1’S “PER PORT” MIB COUNTERS INDIRECT MEMORY OFFSETS
Offset Counter Name Description