Datasheet
2017 Microchip Technology Inc. DS00002348A-page 67
KSZ8873MLL/FLL/RLL
3
Insert SRC Port 2
PVID at Port 1
R/W
1= insert SRC port 2 PVID for untagged frame at
egress port 1
0
2
Insert SRC Port 2
PVID at Port 3
R/W
1= insert SRC port 2 PVID for untagged frame at
egress port 3
0
1
Insert SRC Port 3
PVID at Port 1
R/W
1= insert SRC port 3 PVID for untagged frame at
egress port 1
0
0
Insert SRC Port 3
PVID at Port 2
R/W
1= insert SRC port 3 PVID for untagged frame at
egress port 2
0
Register 195 (0xC3): Power Management and LED Mode
7
CPU Interface Power
Down
R/W
CPU interface clock tree power down enable.
1 = Enable
0 = Disable
Note: Power save a little bit when MII interface is used
and the traffic is stopped in the power management
with normal mode
0
6 Switch Power Down R/W
Switch clock tree power down enable.
1 = Enable
0 = Disable
Note: Power save a little bit when MII interface is used
and the traffic is stopped in the power management
with normal mode
0
5-4 LED Mode Selection R/W
00 = LED0: Link/ACT, LED1: Speed
01 = LED0: Link, LED1: ACT
10 = LED0: Link/ACT, LED1: Duplex
11 = LED0: Link, LED1: Duplex
Note:
Item :: Pin State :: LED Definition
No Link High OFF
Link Low ON
100 Speed Low ON
10 Speed High OFF (Link is ON)
Full-Duplex Low ON
Half-Duplex High OFF (Link is ON)
ACT Toggle Blinking
00
3 LED Output Mode R/W
1 = the internal stretched energy signal from the ana-
log module will be negated and output to LED1 and
the internal device ready signal will be negated and
output to LED0.
0 = the LED1/LED0 pins will indicate the regular LED
outputs.
Note. This is for debugging purpose.
0
2 PLL Off Enable R/W
1 = PLL power down enable
0 = disable
Note: This bit is used in Energy Detect mode with pin
27 MII_LINK_3 pull-up in bypass mode for saving
power
0
1-0
Power Management
Mode
R/W
Power management mode
00 = Normal Mode
01 = Energy Detection Mode
10 = Software Power Down Mode
11 = Power Saving Mode
00
TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Bit Name R/W Description Default