Datasheet
KSZ8873MLL/FLL/RLL
DS00002348A-page 66 2017 Microchip Technology Inc.
Register 186 (0xBA): TXQ Split for Q0 in Port 3
7 Priority Select R/W
0 = enable straight priority with Reg 183/184/185
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
queues with Reg 183/184/185 bits[7]=1.
1
6-0 Reserved RO
Reserved
Do not change the default values.
1
Register 187 (0xBB): Interrupt Enable Register
7-0
Interrupt Enable
Register
R/W
Interrupt enable register corresponding to bits in
Register 188
Note: Set register 187 first and then set register 188
(W1C= Write ‘1’ Clear) to wait the interrupt at pin 35
INTRN for the link to be changed.
0x00
Register 188 (0xBC): Link Change Interrupt
7
P1 or P2 Link
Change (LC)
Interrupt
R/W
Set to 1 when P1 or P2 link changes in analog inter-
face (W1C).
0
6-3 Reserved R/W
Reserved
Do not change the default values.
0
2
P3 Link Change (LC)
Interrupt
R/W Set to 1 when P3 link changes in MII interface (W1C). 0
1
P2 Link Change (LC)
Interrupt
R/W
Set to 1 when P2 link changes in analog interface
(W1C).
0
0
P1 MII Link Change
(LC) Interrupt
R/W
Set to 1 when P1 link changes in analog interface or
MII interface (W1C).
0
Register 189 (0xBD): Force Pause Off Iteration Limit Enable
7-0
Force Pause Off Iter-
ation Limit Enable
R/W
1 = Enable. It is 160 ms before requesting to
invalidate flow control.
0 = Disable
0
Register 192 (0xC0): Fiber Signal Threshold
7
Port 2 Fiber Signal
Threshold
R/W
1 = Threshold is 2.0V
0 = Threshold is 1.2V
0
6
Port 1 Fiber Signal
Threshold
R/W
1 = Threshold is 2.0V
0 = Threshold is 1.2V
0
5-0 Reserved RO
Reserved
Do not change the default value.
0
Register 193 (0xC1): Internal 1.8V LDO Control
7 Reserved RO
Reserved
Do not change the default value.
0
6
Internal 1.8V LDO
Disable
R/W
1 = Disable internal 1.8V LDO
0 = Enable internal 1.8V LDO
0
5-0 Reserved RO
Reserved
Do not change the default value.
0
Register 194 (0xC2): Insert SRC PVID
7-6 Reserved RO
Reserved
Do not change the default value.
00
5
Insert SRC Port 1
PVID at Port 2
R/W
1= insert SRC port 1 PVID for untagged frame at
egress port 2
0
4
Insert SRC Port 1
PVID at Port 3
R/W
1= insert SRC port 1 PVID for untagged frame at
egress port 3
0
TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Bit Name R/W Description Default