Datasheet
2017 Microchip Technology Inc. DS00002348A-page 61
KSZ8873MLL/FLL/RLL
3-2 DSCP[115:114] R/W
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x39.
00
1-0 DSCP[113:112] R/W
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x38.
00
Register 111 (0x6F): TOS Priority Control Register 15
7-6 DSCP[127:126] R/W
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x3F.
00
5-4 DSCP[125:124] R/W
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x3E.
00
3-2 DSCP[123:122] R/W
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x3D.
00
1-0 DSCP[121:120] R/W
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x3C.
00
Registers 112 to 117 contain the switch engine’s MAC address. This 48-bit address is used as the Source Address
for the MAC’s full duplex flow control (PAUSE) frame.
Register 112 (0x70): MAC Address Register 0
7-0 MACA[47:40] R/W — 0x00
Register 113 (0x71): MAC Address Register 1
7-0 MACA[39:32] R/W — 0x10
Register 114 (0x72): MAC Address Register 2
7-0 MACA[31:24] R/W — 0xA1
Register 115 (0x73): MAC Address Register 3
7-0 MACA[23:16] R/W — 0xFF
Register 116 (0x74): MAC Address Register 4
7-0 MACA[15:8] R/W — 0xFF
Register 117 (0x75): MAC Address Register 5
7-0 MACA[7:0] R/W — 0xFF
Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be
used to pass user defined control and status information between the KSZ8873 and the external processor.
Register 118 (0x76): User Defined Register 1
7-0 UDR1 R/W — 0x00
Register 119 (0x77): User Defined Register 2
7-0 UDR2 R/W — 0x00
Register 120 (0x78): User Defined Register 3
7-0 UDR3 R/W — 0x00
Registers 121 to 131 provide read and write access to the static MAC address table, VLAN table, dynamic MAC
address table, and MIB counters.
Register 121 (0x79): Indirect Access Control 0
7-5 Reserved R/W
Reserved
Do not change the default values.
000
4
Read High/Write
Low
R/W
1 = read cycle
0 = write cycle
0
TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Bit Name R/W Description Default