Datasheet

KSZ8873MLL/FLL/RLL
DS00002348A-page 52  2017 Microchip Technology Inc.
1 Count IFG R/W
Count IFG bytes
1 = each frame’s minimum inter frame gap
(IFG) bytes (12 per frame) are included in Ingress and
Egress rate limiting calculations.
0 = IFG bytes are not counted.
0
0 Count Pre R/W
Count Preamble bytes
1 = each frame’s preamble bytes (8 per frame) are
included in Ingress and Egress rate limiting calcula-
tions.
0 = preamble bytes are not counted.
0
Register 22 [6:0] (0x16): Port 1 Q0 Ingress Data Rate Limit
Register 38 [6:0] (0x26): Port 2 Q0 Ingress Data Rate Limit
Register 54 [6:0] (0x36): Port 3 Q0 Ingress Data Rate Limit
7
RMII REFCLK
INVERT
R/W
1: Port 3 inverted refclk selected
0: Port 3 original refclk selected
Note: Bit 7 is available on port 3 in the RLL device.
Other ports and devices will be reserved for this bit.
0
Note: Not
applied to
Reg.38
(Port 2)
6-0
Q0 Ingress Data
Rate Limit
R/W
Ingress data rate limit for priority 0 frames
Ingress traffic from this priority queue is shaped
according to the ingress Data Rate Selected Table.
0
Register 23 [6:0] (0x17): Port 1 Q1 Ingress Data Rate Limit
Register 39 [6:0] (0x27): Port 2 Q1 Ingress Data Rate Limit
Register 55 [6:0] (0x37): Port 3 Q1 Ingress Data Rate Limit
7 Reserved R/W
Reserved
Do not change the default values.
0
6-0
Q1 Ingress Data
Rate Limit
R/W
Ingress data rate limit for priority 1 frames
Ingress traffic from this priority queue is shaped
according to the ingress Data Rate Selected Table.
0
Register 24 [6:0] (0x18): Port 1 Q2 Ingress Data Rate Limit
Register 40 [6:0] (0x28): Port 2 Q2 Ingress Data Rate Limit
Register 56 [6:0] (0x38): Port 3 Q2 Ingress Data Rate Limit
7 Reserved R/W
Reserved
Do not change the default values.
0
6-0
Q2 Ingress Data
Rate Limit
R/W
Ingress data rate limit for priority 2 frames
Ingress traffic from this priority queue is shaped
according to ingress Data Rate Selection Table.
0
Register 25 [6:0] (0x19): Port 1 Q3 Ingress Data Rate Limit
Register 41 [6:0] (0x29): Port 2 Q3 Ingress Data Rate Limit
Register 57 [6:0] (0x39): Port 3 Q3 Ingress Data Rate Limit
7 Reserved RO
Reserved
Do not change the default values.
0
6-0
Q3 Ingress Data
Rate Limit
R/W
Ingress data rate limit for priority 3 frames
Ingress traffic from this priority queue is shaped
according to ingress Data Rate Selection Table.
0
Note: Most of the contents in registers 26-31 and registers 42-47 for ports 1 and 2, respectively, can also be
accessed with the MIIM PHY registers.
Register 26 (0x1A): Port 1 PHY Special Control/Status
Register 42 (0x2A): Port 2 PHY Special Control/Status
Register 58 (0x3A): Reserved, Not Applicable to Port 3
7 Vct 10M Short RO 1 = Less than 10 meter short 0
TABLE 4-7: PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED)
Bit Name R/W Description Default