Datasheet

KSZ8873MLL/FLL/RLL
DS00002348A-page 50  2017 Microchip Technology Inc.
6 Receive Sniff R/W
1 = All packets received on the port will be marked as
“monitored packets” and forwarded to the designated
“sniffer port”
0 = no receive monitoring
0
5 Transmit Sniff R/W
1 = All packets transmitted on the port will be marked
as “monitored packets” and forwarded to the desig-
nated “sniffer port”
0 = no transmit monitoring
0
4 Double Tag R/W
1 = All packets will be tagged with port default tag of
ingress port regardless of the original packets are
tagged or not
0 = do not double tagged on all packets
0
3 User Priority Ceiling R/W
1 = if the packet’s “user priority field” is greater than
the “user priority field” in the port default tag register,
replace the packet’s “user priority field” with the “user
priority field” in the port default tag register.
0 = do not compare and replace the packet’s ‘user pri-
ority field”
0
2-0
Port VLAN
Membership
R/W
Define the port’s egress port VLAN membership. The
port can only communicate within the membership. Bit
2 stands for port 3, bit 1 stands for port 2, bit 0 stands
for port 1.
An ‘1’ includes a port in the membership.
An ‘0’ excludes a port from membership.
111
Register 18 (0x12): Port 1 Control 2
Register 34 (0x22): Port 2 Control 2
Register 50 (0x32): Port 3 Control 2
7
Enable 2 Queue Split
of Tx Queue
R/W
1 = Enable
It cannot be enable at the same time with split 4
queue at register 16, 32, and 48 bit 0.
0 = Disable
0
6
Ingress VLAN
Filtering
R/W
1 = the switch will discard packets whose VID port
membership in VLAN table bits [18:16] does not
include the ingress port.
0 = no ingress VLAN filtering.
0
5
Discard non-PVID
Packets
R/W
1 = the switch will discard packets whose VID does
not match ingress port default VID.
0 = no packets will be discarded
0
4 Force Flow Control R/W
1 = will always enable full-duplex flow control on the
port, regardless of AN result.
0 = full-duplex flow control is enabled based on AN
result.
Pin value during
reset:
For port 1,
P1FFC pin
For port 2,
SMRXD30 pin
For port 3, this
bit has no
meaning. Flow
control is set by
Reg. 6 bit 5.
3
Back Pressure
Enable
R/W
1 = enable port’s half-duplex back pressure
0 = disable port’s half-duplex back pressure
0
TABLE 4-7: PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED)
Bit Name R/W Description Default