Datasheet

KSZ8873MLL/FLL/RLL
DS00002348A-page 46  2017 Microchip Technology Inc.
5
Port 3 Flow Control
Enable
R/W
1 = Enable full-duplex flow control on Switch port 3
MII interface.
0 = Disable full-duplex flow control on Switch port 3
MII interface.
1
Pin P1LED1
strap option.
Pull- up(1):
Enable flow
control
Pull-down(0):
Disable flow
control
Note: P1LED1
has internal pull-
up.
4
Port 3 Speed
Selection
R/W
1 = the Port 3 MII switch interface is in 10 Mbps mode
0 = the Port 3 MII switch interface is in 100 Mbps
mode
0
Pin P3SPD
strap option.
Pull-up(1):
Enable 10 Mbps
Pull-down(0):
Enable
100 Mbps
(default)
Note: P3SPD
has internal pull-
down.
3
Null VID
Replacement
R/W
1 = will replace NULL VID with port VID (12 bits)
0 = no replacement for NULL VID
0
2-0
Broadcast Storm
Protection Rate
Bit [10:8]
R/W
This register along with the next register determines
how many “64 byte blocks” of packet data are allowed
on an input port in a preset period. The period is
67 ms for 100BT or 500 ms for 10BT. The default is
1%.
000
Register 7 (0x07): Global Control 5
7-0
Broadcast Storm
Protection Rate
Bit [7:0]
R/W
This register along with the previous register deter-
mines how many “64 byte blocks” of packet data are
allowed on an input port in a preset period. The period
is 67 ms for 100BT or 500 ms for 10BT. The default is
1%.
Note: 100BT Rate: 148,800 frames/sec * 67 ms/inter-
val * 1% = 99 frames/interval (approx.) = 0x63
0x63
Register 8 (0x08): Global Control 6
7-0 Factory Testing RO
Reserved
Do not change the default values.
0x00
Register 9 (0x09): Global Control 7
7-0 Factory Testing RO
Reserved
Do not change the default values.
0x24
Register 10 (0x0A): Global Control 8
7-0 Factory Testing RO
Reserved
Do not change the default values.
0x35
TABLE 4-6: GLOBAL REGISTERS (0-15) (CONTINUED)
Bit Name R/W Description Default