Datasheet
2017 Microchip Technology Inc. DS00002348A-page 43
KSZ8873MLL/FLL/RLL
4.4 Register Descriptions
192 0xC0 Fiber Signal Threshold
194 0xC2 Insert SRC PVID
195 0xC3 Power Management and LED Mode
196 0xC4 Sleep Mode
198 0xC6 Forward Invalid VID Frame and Host Mode
TABLE 4-6: GLOBAL REGISTERS (0-15)
Bit Name R/W Description Default
Register 0 (0x00): Chip ID0
7-0 Family ID RO Chip family 0x88
Register 1 (0x01): Chip ID1/Start Switch
7-4 Chip ID RO 0x3 is assigned to M series. (73M) 0x3
3-1 Revision ID RO Revision ID —
0 Start Switch R/W
1 = start the switch (default)
0 = stop the switch
1
Register 2 (0x02): Global Control 0
7
New Back-Off
Enable
R/W
New back-off algorithm designed for UNH
1 = Enable
0 = Disable
0
6 Reserved RO Reserved 0
5
Flush Dynamic MAC
Table
R/W
1 = enable flush dynamic MAC table for spanning tree
application
0 = disable
0
4
Flush Static MAC
Table
R/W
1 = enable flush static MAC table for spanning tree
application
0 = disable
0
3
Pass Flow Control
Packet
R/W
1 = switch will pass 802.1x flow control packets
0 = switch will drop 802.1x flow control packets
0
2 Reserved R/W
Reserved
Do not change the default value.
0
1 Reserved R/W
Reserved
Do not change the default value.
0
0 Reserved RO Reserved 0
Register 3 (0x03): Global Control 1
7 Pass All Frames R/W
1 = switch all packets including bad ones. Used solely
for debugging purposes. Works in conjunction with
sniffer mode only.
0
6
Port 3 Tail Tag Mode
Enable
R/W
1 = Enable port 3 tail tag mode.
0 = Disable.
0
5
IEEE 802.3x
Transmit Direction
Flow Control Enable
R/W
1 = will enable transmit direction flow control feature.
0 = will not enable transmit direction flow control fea-
ture. Switch will not generate any flow control
(PAUSE) frame.
1
TABLE 4-5: ADVANCED CONTROL REGISTERS (CONTINUED)
Register (Decimal) Register (Hex) Description