Datasheet

KSZ8873MLL/FLL/RLL
DS00002348A-page 42  2017 Microchip Technology Inc.
4.3 Memory Map (8-Bit Registers)
1
Remote
Loopback
R/W
1 = Perform Remote loopback, as follows:
Port 1 (reg. 26, bit 1 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
Port 2 (reg. 42, bit 1 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 2’s PHY
End: TXP2/TXM2 (port 2)
0 = Normal Operation
0
Reg. 26, bit 1
Reg. 42, bit 1
0 Reserved R/W
Reserved
Do not change the default value.
0—
TABLE 4-3: GLOBAL REGISTERS
Register (Decimal) Register (Hex) Description
0-1 0x00-0x01 Chip ID Register
2-15 0x02-0x0F Global Control Register
TABLE 4-4: PORT REGISTERS
Register (Decimal) Register (Hex) Description
16-29 0x10-0x1D Port 1 Control Registers, including MII PHY Registers
30-31 0x1E-0x1F Port 1 Status Registers, including MII PHY Registers
32-45 0x20-0x2D Port 2 Control Registers, including MII PHY Registers
46-47 0x2E-0x2F Port 2 Status Registers, including MII PHY Registers
48-57 0x30-0x39 Port 3 Control Registers
58-62 0x3A-0x3E Reserved
63 0x3F Port 3 Status Register
64-95 0x40-0x5F Reserved
TABLE 4-5: ADVANCED CONTROL REGISTERS
Register (Decimal) Register (Hex) Description
96-111 0x60-0x6F TOS Priority Control Registers
112-117 0x70-0x75 Switch Engine’s MAC Address Registers
118-120 0x76-0x78 User Defined Registers
121-122 0x79-0x7A Indirect Access Control Registers
123-131 0x7B-0x83 Indirect Data Registers
142-153 0x8E-0x99 Station Address
154-165 0x9A-0xA5 Egress Data Rate Limit
166 0xA6 Device Mode Indicator
167-170 0xA7-0xAA High Priority Packet Buffer Reserved
171-174 0xAB-0xAE PM Usage Flow Control Select Mode
175-186 0xAF-0xBA TXQ Split
187-188 0xBB-0xBC Link Change Interrupt Register
189 0xBD Force Pause Off Iteration Limit Enable
TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED)
Bit Name R/W Description Default Reference