Datasheet
2017 Microchip Technology Inc. DS00002348A-page 33
KSZ8873MLL/FLL/RLL
5. Place the EEPROM on the board and power up the board.
6. Assert an active-low reset to the RSTN pin of the KSZ8873MLL/FLL/RLL. After reset is de-asserted, the
KSZ8873MLL/FLL/RLL begins reading the configuration data from the EEPROM. The KSZ8873MLL/FLL/RLL
checks that the first byte read from the EEPROM is “88”. If this value is correct, EEPROM configuration contin-
ues. If not, EEPROM configuration access is denied and all other data sent from the EEPROM is ignored by the
KSZ8873MLL/FLL/RLL.
For proper operation, ensure that the KSZ8873MLL/FLL/RLL PWRDN input signal is not asserted during the reset oper-
ation. The PWRDN input is active-low.
3.12.2 I
2
C SLAVE SERIAL BUS CONFIGURATION
In managed mode, the KSZ8873MLL/FLL/RLL can be configured as an I
2
C slave device. In this mode, an I
2
C master
device (external controller/CPU) has complete programming access to the KSZ8873MLL/FLL/RLL’s 198 registers. Pro-
gramming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the
“Static MAC Table”, “VLAN Table”, “Dynamic MAC Table,” and “MIB Counters.” The tables and counters are indirectly
accessed via registers 121 to 131.
In I
2
C slave mode, the KSZ8873MLL/FLL/RLL operates like other I
2
C slave devices. Addressing the KSZ8873MLL/FLL/
RLL’s 8-bit registers is similar to addressing the Microchip AT24C02 EEPROM’s memory locations. Details of I
2
C read/
write operations and related timing information can be found in the AT24C02 data sheet.
Two fixed 8-bit device addresses are used to address the KSZ8873MLL/FLL/RLL in I
2
C slave mode. One is for read;
the other is for write. The addresses are as follow:
• 1011_1111 <read>
• 1011_1110 <write>
The following is a sample procedure for programming the KSZ8873MLL/FLL/RLL using the I
2
C slave serial bus:
1. Enable I
2
C slave mode by setting the KSZ8873MLL/FLL/RLL strap-in pins P2LED[1:0] to “01”.
2. Power up the board and assert reset to the KSZ8873MLL/FLL/RLL. Configure the desired register settings in the
KSZ8873MLL/FLL/RLL, using the I
2
C write operation.
3. Read back and verify the register settings in the KSZ8873MLL/FLL/RLL, using the I
2
C read operation.
Some of the configuration settings, such as “Aging Enable”, “Auto Negotiation Enable”, “Force Speed” and “Power
down” can be programmed after the switch has been started.
3.12.3 SPI SLAVE SERIAL BUS CONFIGURATION
In managed mode, the KSZ8873MLL/FLL/RLL can be configured as a SPI slave device. In this mode, a SPI master
device (external controller/CPU) has complete programming access to the KSZ8873MLL/FLL/RLL’s 198 registers. Pro-
gramming access includes the Global Registers, Port Registers, Advanced Control Registers, and indirect access to
the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table,” and “MIB Counters”. The tables and counters are indirectly
accessed via registers 121 to 131.
The KSZ8873MLL/FLL/RLL supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data
write. SPI multiple read and multiple write are also supported by the KSZ8873MLL/FLL/RLL to expedite register read
back and register configuration, respectively.
SPI multiple read is initiated when the master device continues to drive the KSZ8873MLL/FLL/RLL SPISN input pin (SPI
Slave Select signal) low after a byte (a register) is read. The KSZ8873MLL/FLL/RLL internal address counter increments
automatically to the next byte (next register) after the read. The next byte at the next register address is shifted out onto
the KSZ8873MLL/FLL/RLL SPIQ output pin. SPI multiple read continues until the SPI master device terminates it by de-
asserting the SPISN signal to the KSZ8873MLL/FLL/RLL.
Similarly, SPI multiple write is initiated when the master device continues to drive the KSZ8873MLL/FLL/RLL SPISN
input pin low after a byte (a register) is written. The KSZ8873MLL/FLL/RLL internal address counter increments auto-
matically to the next byte (next register) after the write. The next byte that is sent from the master device to the
KSZ8873MLL/FLL/RLL SDA input pin is written to the next register address. SPI multiple write continues until the SPI
master device terminates it by de-asserting the SPISN signal to the KSZ8873MLL/FLL/RLL.
For both SPI multiple read and multiple write, the KSZ8873MLL/FLL/RLL internal address counter wraps back to register
address zero once the highest register address is reached. This feature allows all 198 KSZ8873MLL/FLL/RLL registers
to be read, or written with a single SPI command from any initial register address.
The KSZ8873MLL/FLL/RLL is capable of supporting an SPI bus.