Datasheet

KSZ8873MLL/FLL/RLL
DS00002348A-page 24  2017 Microchip Technology Inc.
• Uses a single 50 MHz clock reference (provided internally or externally).
• Provides independent 2-bit wide (di-bit) transmit and receive data paths.
• Contains two distinct groups of signals: one for transmission and the other for reception
When EN_REFCLKO_3 is high, KSZ8873RLL will output a 50 MHz in REFCLKO_3. Register 198 bit[3] is used to select
internal or external reference clock. Internal reference clock means that the clock for the RMII of KSZ8873RLL will be
provided by the KSZ8873RLL internally and the REFCLKI_3 pin is unconnected. For the external reference clock, the
clock will provide to KSZ8873RLL via REFCLKI_3.
If the reference clock is not provided by the KSZ8873RLL, this 50 MHz reference clock has to be used in X1 pin instead
of the 25 MHz crystal because the clock skew of these two clock sources will impact the RMII timing. The SPIQ clock
selection strapping option pin is connected to low to select the 50 MHz input.
If the reference clock is provided by the KSZ8873RLL, set register 54[7]=1 to invert the RMII reference clock to meet
the timing specification in the worst cases.
The RMII provided by the KSZ8873RLL is connected to the device’s third MAC. It complies with the RMII Specification.
Table 3-6 describes the signals used by the RMII bus. Refer to RMII Specification for full detail on the signal description.
TABLE 3-5: RMII CLOCK SETTING
Reg. 198
Bit[3]
Pin 20 SMTXD33/
EN_REFCLKO_3
Internal Pull-Up
Pin 39 SPIQ
Internal Pull-Up
Clock Source Note
0
0
(pull down by 1 k)
0
(pull down by 1 k)
External 50 MHz OSC input to
SMTXC3/REFCLKI_3 and X1
pin directly
EN_REFCLKO_3 = 0 to
Disable REFCLKO_3 for
better EMI
01
0
(pull down by 1 k)
50 MHz on X1 pin is as clock
source. REFCLKO_3 Output Is
Feedback to REFCLKI_3
externally
EN_REFCLKO_3 = 1 to
Enable REFCLKO_3
01 1
25 MHz on X1 pin is as clock
source. REFCLKO_3 Output is
connected to REFCLKI_3
externally
EN_REFCLKO_3 = 1 to
Enable REFCLKO_3
11 0
50 MHz on X1 pin, 50 MHz RMII
Clock goes to SMTXC3/ REF-
CLKI_3 internally.
REFCLKI_3 can be pulled down
by a resistor.
EN_REFCLKO_3 = 1 to
Enable REFCLKO_3 and
no feedback to
REFCLKI_3
11 1
25 MHz on X1 pin, 50 MHz RMII
Clock goes to SMTXC3/ REF-
CLKI_3 internally.
REFCLKI_3 can be pulled down
by a resistor.
EN_REFCLKO_3 = 1 to
Enable REFCLKO_3 and
no feedback to
REFCLKI_3
TABLE 3-6: RMII SIGNAL DESCRIPTION
RMII Signal Name
Direction (with
respect to PHY)
Direction (with
respect to MAC)
RMII Signal
Description
KSZ8873RLL RMII
Signal Direction
REF_CLK Input Input or Output
Synchronous 50 MHz
clock reference for
receive, transmit, and
control interface
REFCLKI_3 (input)
CRS_DV Output Input
Carrier sense/
Receive data valid
SMRXDV3 (output)
RXD1 Output Input Receive data bit 1 SMRXD31 (output)
RXD0 Output Input Receive data bit 0 SMRXD30 (output)
TX_EN Input Output Transmit enable SMTXEN3 (input)
TXD1 Input Output Transmit data bit 1 SMTXD31 (input)