Datasheet

KSZ8873MLL/FLL/RLL
DS00002348A-page 10  2017 Microchip Technology Inc.
60 P2LED1 Ipu/O
Port 2 LED Indicators:
Default: Speed (refer to register 195 bit[5:4])
Strap option: Serial bus configuration
Port 2 LED Indicators:
Default: Link/Act. (refer to register 195 bit[5:4])
Strap option: Serial bus configuration
Serial bus configuration pins to select mode of access to KSZ8873MLL/FLL/
RLL internal registers.
[P2LED1, P2LED0] = [0, 0] — I
2
C master (EEPROM) mode
(If EEPROM is not detected, the KSZ8873MLL/FLL/RLL will be configured
with the default values of its internal registers and the values of its strap-in
pins.)
Interface Signals Type Description
SPIQ O Not used (tri-stated)
SCL_MDC O I
2
C clock
SDA_MDIO I/O I
2
C data I/O
SPISN I Not used
[P2LED1, P2LED0] = [0, 1] — I
2
C slave mode
The external I
2
C master will drive the SCL_MDC clock.
The KSZ8873MLL/FLL/RLL device addresses are:
1011_1111 <read>
1011_1110 <write>
Interface Signals Type Description
61
P2LED0 Ipu/O
SPIQ O Not used (tri-stated)
SCL_MDC I I
2
C clock
SDA_MDIO I/O I
2
C data I/O
SPISN I Not used
[P2LED1, P2LED0] = [1, 0] — SPI slave mode
Interface Signals Type Description
SPIQ O SPI data out
SCL_MDC I SPI clock
SDA_MDIO I SPI data in
SPISN I SPI chip select
[P2LED1, P2LED0] = [1, 1] – SMI/MIIM mode
In SMI mode, the KSZ8873MLL/FLL/RLL provides access to all its internal 8-
bit registers through its SCL_MDC and SDA_MDIO pins.
In MIIM mode, the KSZ8873MLL/FLL/RLL provides access to its 16-bit MIIM
registers through its SDC_MDC and SDA_MDIO pins.
TABLE 2-1: SIGNALS (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
Description