Datasheet

KSZ8873MLL/FLL/RLL
DS00002348A-page 88  2017 Microchip Technology Inc.
8.0 RESET CIRCUIT
Figure 8-1 shows a reset circuit recommended for powering up the KSZ8873MLL/FLL/RLL if reset is triggered only by
the power supply.
Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example,
the CPU or an FPGA). At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the KSZ8873MLL/
FLL/RLL device. The RST_OUT_N from the CPU/FPGA provides the warm reset after power-up.
FIGURE 8-1: RECOMMENDED RESET CIRCUIT
FIGURE 8-2: RECOMMENDED RESET CIRCUIT FOR CPU/FPGA RESET OUTPUT
VCC
R
10k
C
10μF
D1
KS8873
RST
D1: 1N4148
VCC
R
10k
D2
C
10μF
D1
CPU/FPGA
RST_OUT_n
KS8873
RST
D1, D2: 1N4148