Datasheet

 2017 Microchip Technology Inc. DS00002348A-page 83
KSZ8873MLL/FLL/RLL
7.6 SPI Input Timing
FIGURE 7-13: SPI INPUT TIMING
TABLE 7-6: SPI INPUT TIMING PARAMETERS
Timing
Parameter
Description Min. Typ. Max. Units
f
C
Clock frequency — — 5 MHz
t
CHSL
SPISN inactive hold time 90 — — ns
t
SLCH
SPISN active setup time 90 — — ns
t
CHSH
SPISN active hold time 90 — — ns
t
SHCH
SPISN inactive setup time 90 — — ns
t
SHSL
SPISN deselect time 100 — — ns
t
DVCH
Data input setup time 20 — — ns
t
CHDX
Data input hold time 30 — — ns
t
CLCH
Clock rise time — — 1 µs
t
CHCL
Clock fall time — — 1 µs
t
DLDH
Data input rise time — — 1 µs
t
DHDL
Data input fall time — — 1 µs
SPIQ
SPIC
SPID
SPIS_N
High Impedance
MSB
tCHSL
tSLCH
tDVCH
tCHDX
tDLDH
tDHDL
LSB
tCLCH
tCHCL
tSHCH
tCHSH
tSHSL