Datasheet

 2017 Microchip Technology Inc. DS00002348A-page 77
KSZ8873MLL/FLL/RLL
7.0 TIMING SPECIFICATIONS
7.1 EEPROM Timing
FIGURE 7-1: EEPROM INTERFACE INPUT TIMING DIAGRAM
FIGURE 7-2: EEPROM INTERFACE OUTPUT TIMING DIAGRAM
TABLE 7-1: EEPROM TIMING PARAMETERS
Symbol Parameter Min. Typ. Max. Units
t
cyc1
Clock cycle — 16384 — ns
t
s1
Setup time 20 — — ns
t
h1
Hold time 20 — — ns
t
ov1
Output valid 4096 4112 4128 ns
SCL
SDA
tcyc1ts1 th1
Receive Timing
SCL
SDA
tcyc1
Transmit Timing
tov1