Datasheet

 2017 Microchip Technology Inc. DS00002348A-page 7
KSZ8873MLL/FLL/RLL
26
SMTXC3/
REFCLKI_3
I/O
MLL/FLL: Switch MII transmit clock (MII mode only)
Output in PHY MII mode and SNI mode
Input in MAC MII and RMII mode.
RLL: Reference clock input
Note: Pull-down by resistor is needed if internal reference clock is used in
RLL by register 198 bit 3.
27
SMTXER3/
MII_LINK_3
Ipd
Switch MII transmit error in MII mode
0= MII link indicator from host in MII PHY mode.
1= No link on port 3 MII PHY mode and enable bypass mode.
28 SMRXDV3 Ipu/O
Switch MII receive data valid
Strap option: MII mode selection
PU = PHY mode.
PD = MAC mode (In MAC mode, port 3 MII has to connect a powered active
external PHY for the normal operation)
29
SMRXD33/
REFCLKO_3
Ipu/O
MLL/FLL: Switch MII receive data bit 3/
RLL: Output reference clock in RMII mode.
Strap option: enable auto-negotiation on port 2 (P2ANEN)
PU = enable P2ANEN
PD = disable P2ANEN
30 SMRXD32 Ipu/O
Switch MII receive data bit 2
Strap option: Force the speed on port 2
PU = force port 2 to 100BT if P2ANEN = 0
PD = force port 2 to 10BT if P2ANEN = 0
31 SMRXD31 Ipu/O
Switch MII/RMII receive data bit 1
Strap option: Force duplex mode (P2DPX)
PU = port 2 default to full-duplex mode if P2ANEN = 1 and auto-negotiation
fails. Force port 2 in full-duplex mode if P2ANEN = 0.
PD = Port 2 set to half-duplex mode if P2ANEN = 1 and auto-negotiation fails.
Force port 2 in half-duplex mode if P2ANEN = 0.
32 GND GND Digital ground
33 SMRXD30 Ipu/O
Switch MII/RMII receive data bit 0
Strap option: Force flow control on port 2 (P2FFC)
PU = always enable (force) port 2 flow control feature, regardless of auto-
negotiation result.
PD = port 2 flow control feature is enabled by auto-negotiation result.
34 SCRS3/NC Ipu/O
MLL/FLL: Switch MII carrier sense
RLL: No connection, internal pull-up.
Note: For MLL/FLL part, when chip is configured as MAC mode, this pin
should be driven from CRS pin of PHY or from CRS pin of FPGA with a logic
of (TXEN | RXDV). If only full-duplex is used, then this pin should be pull-
down by 1k resistor.
35 SCOL3/NC Ipu/O
MLL/FLL: Switch MII collision detect
RLL: No connection, internal pull-up.
TABLE 2-1: SIGNALS (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
Description