Datasheet

 2017 Microchip Technology Inc. DS00002348A-page 63
KSZ8873MLL/FLL/RLL
6-0
Q0 Egress Data
Rate Limit
R/W
Egress data rate limit for priority 0 frames
Egress traffic from this priority queue is shaped
according to Ta b le 4- 8 .
0
Register 155[6:0] (0x9B): Port 1 Q1 Egress Data Rate Limit
Register 159[6:0] (0x9F): Port 2 Q1 Egress Data Rate Limit
Register 163[6:0] (0xA3): Port 3 Q1 Egress Data Rate Limit
7 Reserved R/W
Reserved
Do not change the default values.
0
6-0
Q1 Egress Data
Rate Limit
R/W
Egress data rate limit for priority 1 frames
Egress traffic from this priority queue is shaped
according to Ta b le 4- 8 .
0
Register 156[6:0] (0x9C): Port 1 Q2 Egress Data Rate Limit
Register 160[6:0] (0xA0): Port 2 Q2 Egress Data Rate Limit
Register 164[6:0] (0xA4): Port 3 Q2 Egress Data Rate Limit
7 Reserved R/W
Reserved
Do not change the default values.
0
6-0
Q2 Egress Data
Rate Limit
R/W
Egress data rate limit for priority 2 frames
Egress traffic from this priority queue is shaped
according to Ta b le 4- 8 .
0
Register 157[6:0] (0x9D): Port 1 Q3 Egress Data Rate Limit
Register 161[6:0] (0xA1): Port 2 Q3 Egress Data Rate Limit
Register 165[6:0] (0xA5): Port 3 Q3 Egress Data Rate Limit
7 Reserved R/W
Reserved
Do not change the default values.
0
6-0
Q3 Egress Data
Rate Limit
R/W
Egress data rate limit for priority 3 frames
Egress traffic from this priority queue is shaped
according to Ta b le 4- 8 .
0
Register 166 (0xA6): KSZ8873 Mode Indicator
7-0
KSZ8873 Mode
Indicator
RO
bit7: 1 = Reserved
bit6: 1 = 48P pkg of 2 PHY mode
bit5: 1 = Reserved 0 = Reserved
bit4: 1 = Port 3 RMII 0 = Port 3 MII
bit3: 1 = Reserved 0 = Reserved
bit2: 1 = Port 3 MAC MII 0 = Port 3 PHY MII
bit1: 1 = Port 1 Copper 0 = Port 1 Fiber
bit0: 1 = Port 2 Copper 0 = Port 2 Fiber
0x03 MLL
0x13 RLL
0x00 FLL
Register 167 (0xA7): High Priority Packet Buffer Reserved for Q3
7-0 Reserved RO
Reserved
Do not change the default values.
0x45
Register 168 (0xA8): High Priority Packet Buffer Reserved for Q2
7-0 Reserved RO
Reserved
Do not change the default values.
0x35
Register 169 (0xA9): High Priority Packet Buffer Reserved for Q1
7-0 Reserved RO
Reserved
Do not change the default values.
0x25
Register 170 (0xAA): High Priority Packet Buffer Reserved for Q0
7-0 Reserved RO
Reserved
Do not change the default values.
0x15
Register 171 (0xAB): PM Usage Flow Control Select Mode 1
7 Reserved RO
Reserved
Do not change the default values.
0
TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Bit Name R/W Description Default