Datasheet

KSZ8873MLL/FLL/RLL
DS00002348A-page 62  2017 Microchip Technology Inc.
3-2 Table Select R/W
00 = static MAC address table selected
01 = VLAN table selected
10 = dynamic MAC address table selected
11 = MIB counter selected
00
1-0
Indirect Address
High
R/W Bits [9:8] of indirect address 00
Register 122 (0x7A): Indirect Access Control 1
7-0 Indirect Address Low R/W
Bits [7:0] of indirect address. Note: A write to register
122 triggers the read/write command. Read or write
access is determined by register 121 bit 4.
0000_0000
Register 123 (0x7B): Indirect Data Register 8
7 CPU Read Status RO
This bit is applicable only for dynamic MAC address
table and MIB counter reads.
1 = read is still in progress
0 = read has completed
0
6-3 Reserved RO Reserved 0000
2-0 Indirect Data [66:64] RO Bits [66:64] of indirect data 000
Register 124 (0x7C): Indirect Data Register 7
7-0 Indirect Data [63:56] R/W Bits [63:56] of indirect data 0000_0000
Register 125 (0x7D): Indirect Data Register 6
7-0 Indirect Data [55:48] R/W Bits [55:48] of indirect data 0000_0000
Register 126 (0x7E): Indirect Data Register 5
7-0 Indirect Data [47:40] R/W Bits [47:40] of indirect data 0000_0000
Register 127 (0x7F): Indirect Data Register 4
7-0 Indirect Data [39:32] R/W Bits [39:32] of indirect data 0000_0000
Register 128 (0x80): Indirect Data Register 3
7-0 Indirect Data [31:24] R/W Bits [31:24] of indirect data 0000_0000
Register 129 (0x81): Indirect Data Register 2
7-0 Indirect Data [23:16] R/W Bits [23:16] of indirect data 0000_0000
Register 130 (0x82): Indirect Data Register 1
7-0 Indirect Data [15:8] R/W Bits [15:8] of indirect data 0000_0000
Register 131 (0x83): Indirect Data Register 0
7-0 Indirect Data [7:0] R/W Bits [7:0] of indirect data 0000_0000
Register 147~142 (0x93~0x8E): Station Address 1 MACA1
Register 153~148 (0x99~0x94): Station Address 2 MACA2
47-0 Station Address R/W
48-bit Station address MACA1 and MACA2.
Note: The station address is used for self MAC
address filtering, see the port register control 5 bits
[6,5] for detail.
48’h0
Note: the MSB
bits[47-40] of
the MAC is the
register 147 and
153. The LSB
bits[7-0] of MAC
is the register
142 and 148.
Register 154[6:0] (0x9A): Port 1 Q0 Egress Data Rate Limit
Register 158[6:0] (0x9E): Port 2 Q0 Egress Data Rate Limit
Register 162[6:0] (0xA2): Port 3 Q0 Egress Data Rate Limit
7
Egress Rate Limit
Flow Control Enable
R/W
1 = enable egress rate limit flow control.
0 = disable
0
TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Bit Name R/W Description Default