Datasheet

KSZ8873MLL/FLL/RLL
DS00002348A-page 56  2017 Microchip Technology Inc.
2 Operation Speed RO
1 = link speed is 100 Mbps
0 = link speed is 10 Mbps
0
1 Operation Duplex RO
1 = link duplex is full
0 = link duplex is half
0
0 Far-End Fault RO
1 = far-end fault status detected
0 = no far-end fault status detected
0
Note: This bit is
applicable to
port 1 and port 2
for FLL part
only.
Register 67 (0x43): Reset
4 Software Reset R/W
1 = Software reset
0 = Clear
Note: Software reset will reset all registers to the initial
values of the power-on reset or warm reset (keep the
strap values).
0
0PCS Reset R/W
1 = PCS reset is used when is doing software reset
for a complete reset
0 = Clear
Note: PCS reset will reset the state machine and
clock domain in PHY’s PCS layer.
0
TABLE 4-8: DATA RATE LIMIT
Data Rate Limit for
Ingress or Egress
100BT
Register Bit[6:0], Q = 0...3
10BT
Register Bit[6:0], Q = 0...3
—
1 to 0x63 for 1 Mbps to 99 Mbps Rate 1 to 0x09 for 1 Mbps to 9 Mbps Rate
0 or 0x64 for 100 Mbps Rate 0 or 0x0A for 10 Mbps Rate
64 kbps 0x65
128 kbps 0x66
192 kbps 0x67
256 kbps 0x68
320 kbps 0x69
384 kbps 0x6A
448 kbps 0x6B
512 kbps 0x6C
576 kbps Data 0x6D
640 kbps 0x6E
704 kbps 0x6F
768 kbps 0x70
832 kbps 0x71
896 kbps 0x72
960 kbps 0x73
TABLE 4-7: PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED)
Bit Name R/W Description Default