Datasheet
2017 Microchip Technology Inc. DS00002348A-page 51
KSZ8873MLL/FLL/RLL
2 Transmit Enable R/W
1 = enable packet transmission on the port
0 = disable packet transmission on the port
Note: This bit is used for spanning tree support.
1
1 Receive Enable R/W
1 = enable packet reception on the port
0 = disable packet reception on the port
Note: This bit is used for spanning tree support.
1
0 Learning Disable R/W
1 = disable switch address learning capability
0 = enable switch address learning
Note: This bit is used for spanning tree support.
0
Register 19 (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
7-0 Default Tag [15:8] R/W
Port’s default tag, containing
7-5 = User priority bits
4 = CFI bit
3-0 = VID[11:8]
0x00
Register 20 (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Register 52 (0x34): Port 3 Control 4
7-0 Default Tag [7:0] R/W Port’s default tag, containing 7-0: VID[7:0] 0x01
Note: Registers 19 and 20 (and those corresponding to other ports) serve two purposes:
Associated with the ingress untagged packets, and used for egress tagging.
Default VID for the ingress untagged or null-VID-tagged packets, and used for address lookup.
Register 21 (0x15): Port 1 Control 5
Register 37 (0x25): Port 2 Control 5
Register 53 (0x35): Port 3 Control 5
7
Port 3 MII Mode
Selection
R/W
1 = Port 3 MII MAC mode
0 = Port 3 MII PHY mode
Note: Bit 7 is reserved in the port 1 and port 2 of the
port register control 5. But its recommended to set the
register 21 port 1 control 5 bit [7] = ‘1’ for better EMI,
because this bit 7 of the register 21 is for port 1 MII of
the MML part. In the MLL/FLL/RLL parts, setting this
bit will disable the unused internal 25 MHz clock for
the unused port 1 MII PHY mode circuits.
Inversion of
power strapped
value
of SMRXDV3
6
Self-Address Filter-
ing Enable MACA1
(not for 0x35)
R/W
1 = enable port 1 self-address filtering MACA1
0 = disable
0
5
Self-Address Filter-
ing Enable MACA2
(not for 0x35)
R/W
1 = enable port 2 self-address filtering MACA2
0 = disable
0
4
Drop Ingress Tagged
Frame
R/W
1 = Enable
0 = Disable
0
3-2 Limit Mode R/W
Ingress Limit Mode
These bits determine what kinds of frames are limited
and counted against ingress rate limiting.
00 = limit and count all frames
01 = limit and count Broadcast, Multicast, and flooded
unicast frames
10 = limit and count Broadcast and Multicast frames
only
11 = limit and count Broadcast frames only
00
TABLE 4-7: PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED)
Bit Name R/W Description Default